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Why does selecting a new bitfile cause FPGA VI Reference to show a coercion dot?

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This happens when the data cluster within that reference does not match that of the control or indicator. Front panel items, memory items, FIFOs, etc. and their data types are all contained within that reference wire and if they don't match between the sink and the source, it will coerce it.

 

To fix this problem, make sure all the FPGA VI items match perfectly between inputs and outputs you are trying to wire together.

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