Why does the compiler use LUTs to implement multipliers instead of using the pre-built multipliers (DSP48Es) ?

[SunJab]

Hi everyone,

I am using NI PXI 7842R (Virtex-5 LX50) FPGA. I have implemented two 17 tap direct form FIR filters in labview FPGA. One is used to filter the I channel data and other is used to filter the Q channel data. These filtered IQ outputs are then fed to the 'FFT Express VI' configured for length 16, input data type (s,16,-2), output data type (s,21,3), throughput:1 cycle/sample and execution mode set to single-cycle timed loop. When I compile the FPGA code, the compiler instead of implementing the FIR filter multipliers (17 x 2 = 34) using DSP48Es,  implements using LUTs and shows only 8 of DSP48Es used (probably used by the FFT VI ). I'm using Fixed Point Math Library 'multiplier' function with "implement using LUTs" option unchecked.

All of the multipliers are implemented using DSP48Es if i compile the FIR filters and FFT VI seperetely. But when I integrate the two in a single VI and compile it implements using LUTs.

Any ideas...why i'm facing this problem? 

Thanks

[JLewis]

The High Throughput Multiply doesn't force the use of DSP48E blocks, but leaves it to the discretion of the Xilinx synthesis tools, which may change the implementation based on overall resource usage. If the filter coefficients are constants, then they are more likely to be implemented as LUTs since there are optimizations available to avoid unnecessary computations for small constants or zeroes within a constant. If the FPGA begins to get full, the compiler should attempt to switch to use available resources. Sometimes it has a problem when DSP48Es are scarce, but I'm not aware of any issues switching from DSP48Es to LUTs.

Is this a problem for your current design, or are you just concerned about running out of space later?