Why is my shift register changing my data type from single to double?

[Frenk]

I am programming for a real-time target, and would like to maintain type single for my data.

I have a VI with a number of shift registers. One of the shift registers keeps forcing my type single to double, whereas the other does not!

Can anyone explain this behaviour? Is this a bug?

Thanks in advance,
Frenk

[Ben]

I do not have LV7 loaded so I can not tell you where in your diagram the issue is.

I do not believe this is a bug!

LV will adapt the SR's to handle the most demanding data type wired to the SR.

I suspect that one of the nodes you have wired to that SR is a double.

Show your help window and then switch to your wiring tool. Position your wiring tool over each of the wires that feed your SR and watch your help window. It will show you the data type of the wire. If you check all of the wire that feed that SR you will find one that is a DBL.

You can then insert a "numeric>>>conversion>>>to single..." to fix this issue.

I hope this helps,

Ben

[Frenk]

Hello,
Thank you for your suggestion. I have already looked through the diagram, and the only types I introduce are single.

Its quite strange: if I remove the offending shift register, all the wires are single as they should be. As soon as I add a new shift register, a host of single to double conversions trickle through my code!

I need to avoid the conversion to double, because this code is called for every data point in a real-time acquisition.

Any other suggestions would be greatly appreciated!
Thanks,
Frenk

[Ben]

I just looked at your code on another developer's machine using LV7.

Your math node are retuning DBL's!

Please follow the instructions I provided in my original answer and you will see the output of your "add" etc are returning DBL's.

This is not a bug! This is how LV works.

Rather than coercing to SGL's, I suggest you use DBL's to avoid the coercion of the results coming from your math nodes.

Ben

[Frenk]

Ben,
Thank you for your effort. It is clear that there is something happening here that I don't understand.

If you remove the shift register, you will notice that the math operations (add, multiply) do return single values! Its only when the shift register is added, that the doubles trickle across that wire! (To do this without broken wires, you would need to connect a single constant to the left input side of the case structure).

Also, I've noticed that if I put a conversion to single just before the shift register on the right side of the case structure, that ALL the conversions to double disappear in the case structure.

I really want to avoid double because my data are collected as single, and the conversion to double would occur
with each data point, at some cost (albeit small) to the real-time operation.

If you could explain the effects in my first two paragraphs above, I'd be grateful!
Thanks again,
Frenk

[Ben]

Please see the attached VI for a detailed step by step illustration of what is happening.

The point I believe you have been missing is that "tunnels" have a data type AND the left SR terminal is the same type as the right.

Trying to help,

Ben

[Ben]

I believe the example I posted answers your question, but Now have a chance to look at your example using LV7.

The coercion behaviour shown in your diagram I simply can not explain!

I may have been wrong when I said this was not a bug! I say may because ther have been many times when I was not able to explain a behaviour that I thought is was a bug.

The part I can not explain is illustrated in the LV 6.1 version of your code that I modified. It turns out that if you insert a "to SGL..." into the bottom wire feeding the subtract node, ALL OF THE COERCION DOTS GO AWAY!

My best guesses are;
1) The default data typeof the subtract or Index array is being used AND the help window AND coercion dots are lying t
o us.
2) While completing the wiring to the output tunnel from the subtract node, the data type of the output tunnel is undefined and LV defaluts it to a DBL.
3) Least likely, the Multiply nodes are confussing the data types.

I will post a question using this example to the LV General forum because I can get a wider audience there and this is not a LV-RT specific Q.

I will let you know if I figure this one out.

Ben

[Ben]

The new Q I posted is here.

http://exchange.ni.com/servlet/ProcessRequest?RHIVEID=101&RPAGEID=135&HOID=50650000000800000074B90000&USEARCHCONTEXT_CATEGORY_0=_49_%24_6_&USEARCHCONTEXT_CATEGORY_S=0&UCATEGORY_0=_49_%24_6_&UCATEGORY_S=0

Ben

[Frenk]

Ben,

Thank you for all your work! I took the weekend off, and am grateful that you put so much effort into this! I was surprised to see such a large thread treating the problem.

I'll continue to follow the labview general thread.

Best Regards,
Frenk

[Ben]

Please see this Q on LV General

http://exchange.ni.com/servlet/ProcessRequest?RHIVEID=101&RPAGEID=135&HOID=50650000000800000074B9000...

Using this command in the LV ini file

defprecision=Single

changes the behaviour to what you would expect.

Ben


Ben Rayner
Certified LabVIEW Developer
www.DSAutomation.com