I was wondering if I am overlooking something regarding wiring an error cluster into a logic gate. I am referring to a similar feature as wiring the error cluster into a case structure select or a while loop stop control.
Is this not implemented for logic gates? It does not appear to be (at least in LV 7.0 / 7.1) This would be a nice feature to have rather than having to breakout the cluster elements to get the status.