Wiring the loop condition terminal in an SCTL

[VIM18]

Hi, all.

I'm fairly new to LabVIEW, and I've a bit of a doubt with the loop condition terminal that I suspect is pretty basic. When using a While loop, the VI breaks if there's no condition wired to the terminal, even if this be a constant T. The same is also pretty explicitly mentioned here, and I think that makes perfect sense.

Now, I'm looking at some LabVIEW FPGA code on a forum post I was going through to understand SCTLs better (the attached picture is NOT my own code, credits to Mahesh0459), and the conditional terminal in the SCTLs doesn't seem to be wired. When I watched the video that introduced this concept, a While loop was shown to be directly replaced with an SCTL, as a result of which the constant F (from the While loop) was automatically wired to the terminal.

So, my question is this: is it okay to leave the loop condition terminal unwired in an FPGA VI? If so, what is the reason? Or, is this behaviour specific only to SCTLs? If so, again, what is the reason?

Thanks!

[crossrulz · Accepted solution]

Only in FPGA is it fine.  The reason being that it is assumed the loop will just run forever in the hardware.  Not having the loop check saves some gates.

[VIM18]

Thank you, crossrulz! 

In addition, a more generic doubt regarding the nature of loops in general. When a wait of, say, 5 ms is enclosed in a While loop, the loop is generally seen to execute every 5 ms. However, if there is a particularly intensive segment of code that itself takes, say, 6 ms to execute, would that make the 5 ms wait as a result of the dataflow paradigm, or will the loop now execute once every 11 ms, or somewhere in between?

[crossrulz]

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@VIM18 wrote:

In addition, a more generic doubt regarding the nature of loops in general. When a wait of, say, 5 ms is enclosed in a While loop, the loop is generally seen to execute every 5 ms. However, if there is a particularly intensive segment of code that itself takes, say, 6 ms to execute, would that make the 5 ms wait as a result of the dataflow paradigm, or will the loop now execute once every 11 ms, or somewhere in between?

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Depends on how it is wired.  If the wait is in parallel with the rest of the code in the loop, then the wait and the processing happen in parallel.  Therefore the loop rate in your example will just be the 6ms for the code to execute.

[VIM18]

Cool, thanks for your time!