02-16-2018 05:18 PM
What is the actual hardware you are using for output? I also notice that there are two coercion dots in your code. You should try using explicit datatype conversions on these to convert the datatype to the type expected by your function inputs, instead of having the functions perform the coercion.
What does the analog output function expect in terms of data range? Engineering units in Volts? or something else?
02-16-2018 06:41 PM
First of all, thanks for providing such a valuable input.
I think that processing can be done on FPGA instead of RT if we use fixed point data type but I already tried that and I was not successful. I tried using two loops in the FPGA code with fixed point data type, one loop was for data acquisition which was running at 40 MHz and another loop for wrtiting data to analog pin which was a while loop with 100 ms wait time. But it didn't work out. Can you suggest something?
The reason I used extended precision was that I need to multiply no. of ticks with a number 2.5 x 10^-8 (because the frequency of FPGA clock is 40 MHz). I verified that I am getting correct frequency readings so I do not think there is any problem with data acquisition.
Talking about hardware, I am using My-RIO and I have used it before at fastest loop rate of 1 ms and it worked perfectly fine. Signal is between 0 to 60 KHz so I can not use while loop (which can acquire data at maximum rate of 1KHz, correct me if I am wrong). I checked the manual of My-RIO and found out that maximum PWM frequency of DI/O is 100KHz and for SPI it can go upto 4 MHz. Aggregate maximum update rates for Analog pin is 345 kS/s. Do you recommend updating the loop rates? If yes, what should be the loop rates in FPGA code for the two?
Lets consider I am not writing the data to analog channel in FPGA VI instead I am using RT to do so, that's what I showed in previous post. Also, as you suggested to remove the local variable and update the front the panel every 100 ms, I used the same, to write data to Analog channel except I didn't use FIFO. Can I write data to analog channel in the same loop updating every 100 ms? Why do I need FIFO if I am concerned about only the latest data? What could be the possible cause of error in that? Why was it not writing anything to analog pin?
Refering to the timed loop in RT. Now I am using a while loop instead to write data to analog channel. However, I can still check finished late node to reduce my loop rate. But the point is why do I need to do that? I am fine writing data at 1KHz frequency or less, so I don't need a timed loop. What do you suggest?
I tried to put data type conversion, that didn't work either.
Analog Output function is an Express VI which writes Voltage to analog pin based on data provided by user ranging from 0 to 10 Volts.
Thanks and Regards,
Kashish Dhal
02-16-2018 06:58 PM
Also, I don't know that how to change loop rate in FPGA. The only method I can think of is wait function. Please help me with this as well.
Regards,
Kashish Dhal
02-16-2018 07:29 PM
There is a wait function in the FPGA palette. Is uses a digital counter to delay the loop using the clock divided by the specified wait interval.