Xilinx FPGA Decoder IP Not Generating

[aschwirian]

Hello all,

I am trying to use the Polar and LDPC Xilinx IP cores that are available in LabVIEW FPGA. I have the licensing files set up correctly, and I am able to generate the Encoding side with no problems. If I attempt to create a Decoder for either the Polar or LDPC cores though, the IP generation process will become unresponsive after the step "Built XSI simulation shared library xsim.dir" (see attachment). I've tried waiting and let the process run, but it remained unresponsive even after 14 hours. Neither of the Polar coding memory options (distributed RAM or BRAM) has been able to complete the generation process.

Are there any suggestions for being able to successfully generate the Decoder?

[Terry_ALE]

Which NI FPGA product are you using, which version of LabVIEW, and which windows OS are you using?

[aschwirian]

Good question, this is being compiled for a USRP X310 so the FPGA is a Xilinx Kintex-7 XC7K410T. I am using LabVIEW 2020 on a Windows 10 system.

[aschwirian · Accepted solution]

For completeness, this error has been confirmed to exist and a workaround for this problem has been found. The accepted solution is to generate the necessary IP in Vivado and then import it into LabVIEW with an IP Integration Node. This solution has worked for both the Polar and LDPC decoder IPs.

[Terry_ALE]

Glad you have a solution.

Never had to do this with the ip blocks that come with LabVIEW.

I did not expect going to Vivado to have been needed.