acquiring input from crio in fpga mode

[Davidek]

Hi Again

Sorry for not getting back to you sooner. I've had a look at your code and I'm a bit confused. From your post and now seeing your code it feels to me you're confusing the use of LV FPGA with the use of DAQmx. The architechtures are completely different so just trying to input the channel name you want to acquire the frequency from to the Open FPGA VI Reference will not work. As the name suggest the Open FPGA VI Reference opens a reference to a VI, not a channel on a module in the cRIO chassis. The FPGA VI itself is also straight from the example and will not measure the frequency of an analog input signal. You'll need to recode it from scratch.

With LV FPGA you'll need to define which channels from which modules to read in the FPGA VI. You do this with FPGA I/O nodes. You can then used a finished block avaliable under FPGA Math and Analysis in the palette to calculate the period of the signal. This is how part of the code can look:

 

You will then need to create a RT host VI that reads the data from the FPGA VI. You do this by opening a reference to the FPGA VI (With the Open FPGA VI Reference.vi) and then reading the data via a Read/Write Control. You can see how this is done in the VI you already sent me. What appears in the Read/Write Controls depends on what the FPGA VI has on it's front panel.

There is also a completly different option and that is to not use LV FPGA at all, but to use only LV Real-time and run the FPGA via Scan Engine. The advantage is that it is simpler and faster coding, but you take a hit in performance. You also need to have a cRIO controller that can handle Scan Engine. You can find examples in the Example Finder under Hardware Input and Output-> CompactRIO->NI Scan Engine

Best Regards

David

Message Edited by Davidek on 03-17-2010 08:28 AM

[johnnewton]

Hi David,

Thanks for the reply,

I followed your instructions and it worked fine. Kudos!!

Unfortunately in my application I need to calculate digital period and I had been trying yesterday to create a vi. Please have a look in my digital period fpga and digital period host vi. I believe I am nearly there but not using function of tick count properly. Any suggestions!!!

[Davidek]

Hi

I had a look at your code. I'm not sure what you mean by digital period because that normally involves a digital pulse train, not an analog signal. Is the analog signal you are trying to measure in reality a digital signal? What are you after? The actual time period? You can calculate that from the code I posted in the same way as you do now in your host VI. Number of samples * loop rate. (You are assuming 40 MHz loop rate in your code at the moment).

Also, in your FPGA code you don't initialize any of you shift registers. This can lead to enexpected behavior in the code.

On the RT host side I strongly recommend you implement a dual loop architechture. Read the data in one loop, transfer it with a RT FIFO or a queue to a second loop and write to file in that loop. The way you have it know the rate of the RT VI is going to be very slow compared to the FPGA VI as File I/O is a comparatively slow operation.

Also, RT VIs normally only have User interfaces for debugging. There is no screen output from the cRIO, right? So what you are doing at the moment when you run your RT VI is that you send all the commands and data back and forth between your computer and the cRIO via ethernet. The determinism of the RT VI is destroyed and it puts an extra strain on the CPU on the RT controller. This is fine for testing and development, but not for actual deployment.

Best Regards

David

PS. Saying Kudos is not the same as giving kudos.... DS.

Message Edited by Davidek on 03-17-2010 11:22 AM