Hi hang-up,
It looks like you are specifying the loop rate for the entire while loop you are in, and not just that one specific part of code. Because you have your loop timer controlled by an front panel object, it is possible that the code compiled, but if you change the loop time to a low value, the code cannot complete in time. I would suggest that you isolate the acquisition you are trying to do in it's own loop so that it can run at full speed.
Additionally, in order to get the full MS/s acquisition, you are going to need to architect your acquisition. I would encourage you to check out the example code in our Example Finder for the NI 9223 User Controlled II Compositionally for the best way to get these maximum acquisition rates. Additionally, depending on how you are going to be exporting this data from the FPGA, your ART controller may not be able to handle a sustained MS/s throughput.
To explicitly answer your question, I suspect that because you are trying to complete a large loop in a short amount of time, the FPGA cannot complete the task in time, so it defaults to a rate that can be better handled. For the control you are looking for, I would encourage you to move your application over to the architecture found in the example project to get the behavior you are looking for.
