cRIO Consumer Producer FPGA RT 100 kHz

[amazzeo]

David,

     Thank you for the response.  These are good answers.  I have been able to run the FPGA with a consistent clock tick of 400 (10 us) by taking out two of the A to D input channels I was using.  For my application I do not need all four.

     I may get around to trying your suggestion for changing over to the raw format.  I suspect that might help me with speed.

Aaron

[David_L]

Glad to hear this worked.

[MrBliss]

Hi

Did you manage to get this to work properly for your application.

I need to read 5 channels from 2 9215 modules running at least 50mhz perferably higher

I am struggling to get the data out of the fifo buffer in time and store it to binary file in the rt (9024)

Thanks

Mark

[T-REX$]

Hello Mark,

It looks like this thread has been dead for a number of months now, and looking through it, I believe your answer is yes, he did get this working. As far as your 50MHz clock rate, this is not remotely possible with your setup. Did you mean 50KHz? If so, I would try a producer consumer loop on the RT side to read all available elements out of your FIFO, then write them to binary in the consumer loop. If you need further help with your application, you might have better luck starting a new thread. I imagine no-one previously involved in this thread still monitors it's activity.