cRIO FPGA bus traffic rate?

[RonW]

My question is about bandwidth being used up by FPGA loops that are free running, i.e. they don't have loop timers.

A couple of illustrative examples:

1. A simple loopback: A free running loop in the FPGA that connects an input terminal from the controller to an output terminal back to the controller. The idea is that the controller can set the input terminal, then monitor the output terminal to ensure that it changes.

2. An output: A free running loop in the FPGA that connects an input terminal from the controller to a digital output module. The idea is that the controller can set the digital output whenever it wants.

My question is, does these free running loops use up significant bandwidth in the system by constantly accessing the terminals (and modules) if the controller only accesses the terminals occasionally? Or is bus traffic dictated by how often the controller (rather than the FPGA) accesses the shared terminals? My concern is that the FPGA constantly accessing the shared terminals might eat into the bandwidth available for data transfer between the FPGA and the controller.

And yes, there is a reason I'd rather not put loop timers in, "just in case".

Thanks.

[CharlieM]

Hi Ron,

The terminals of a loop are only used once. The controller cannot constantly monitor the output terminal of a loop because no value will pass out of the terminal until the loop is finished. You will need code within the loop to pass data in-between the controller and the FPGA.

I would recommend opening example programs to see how others have approached similar applications. Also, if you are concerned about delays caused by the communication between the controller and the FPGA, you may want to use tick counters within the loop to display how fast you are looping.

[JMota]

RonW,

As far as I understand things, this is the true statement: "bus traffic dictated by how often the controller (rather than the FPGA) accesses the shared terminals". That is, if you never read or write to those controls/indicators from the controller, it will have no performance impact on the data transfer between the FPGA and the controller.

JMota

[Bassett_Hound]

Hi Ron,

The FPGA VI and the host VI are inherently asynchronous and having a free running FPGA loop will not affect the read/write speeds of indicators/controls in the loop.  The LabVIEW FPGA Module creates a register map, specific to the FPGA VI, that includes a hardware register for every control and indicator. LabVIEW then uses the register map internally to communicate with the FPGA VI directly which is basically just reading the controls/indicator register.  So as you mentioned reading the controls and indicators is really dictated by the Controller and not the FPGA.  However, if your using DMA, then the FPGA can affect the data transfer as it would then be stuffing data into the pipe line.

Under FPGA Module Concepts there are a couple documents you would be interested called "Transferring Data Between the FPGA and Host VI" and "Synchronizing the FPGA and the Host VI" that will give a little better understanding.

Regards,

Bassett