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cluster as a input to subvi

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@N_743 wrote:

Hi Altenbach,

 

I meant to say what if they are in different loops or cases and not in sequence (in-line) to each other. Language gap.


I think that you need to show us what you have done and what you want to achieve. It sounds like your problem has less to do with getting data into a subvi and more to do with passing data between loops or from one iteration of a loop to the next (which is what I'm assuming that you are referring to when you say cases). 

 

Have you gone through any of the LabVIEW tutorials? 

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Hi Johntrich,

 

You got the wrong guy. You will have to say this to the person in the first post, jeet4230.


Have you gone through any of the LabVIEW tutorials? 


Yes, I have and completed core 1,2,3, Advanced Architecture, RT and FPGA.

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@N_743 wrote:

Hi Johntrich,

 

You got the wrong guy. You will have to say this to the person in the first post, jeet4230.


Have you gone through any of the LabVIEW tutorials? 


Yes, I have and completed core 1,2,3, Advanced Architecture, RT and FPGA.


Okay now I am lost here, I guess it's my fault for not paying attention. I didn't notice  N_743 wrote "What if it is not in-line." and pulled this entire thread off the OP topic.

 

jeet4230, did we answer your question?

 

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=== Engineer Ambiguously ===
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@N_743 wrote:

I meant to say what if they are in different loops or cases and not in sequence (in-line) to each other. Language gap.


Well, that's an architectural problem and we cannot help unless you provide significantly more detail.

(A "loop" is very different from a "case", for example)

.

Where does the cluster come from and where is its data kept (e.g. shift register). Does it matter in what order the subVI is called? What should happen with the output of the subVI? Is it reentrant or not?

 

You can place a subVI as many times as you want on the same diagram. The rest is all in the dataflow, of course.

 

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@N_743 wrote:

Hi Johntrich,

 

You got the wrong guy. You will have to say this to the person in the first post, jeet4230.


Have you gone through any of the LabVIEW tutorials? 


Yes, I have and completed core 1,2,3, Advanced Architecture, RT and FPGA.


As nobody of us understood the OPs request in the first place, it would seem at least unwise for you to jump on this thread and capture it for your own, rather short-hand questions that seem not necessarily related to the initial request anyways.

 

So don't be surprised if you get answers that convolute your issue with the initial request.

 

There are people here using multiple accounts for whatever reason, so a different user name doesn't automatically mean that it is a different user, or it is a colleague following up and knowing about the original problem in detail and assuming that our understanding of their problem must be at least as complete, so that long explanations and posting of actual code that shows the discussed problem/difficulty are nothing more than a waste of effort. 😀

 

But when you post a problem/question here, you have to always assume that we know absolutely nothing about your problem and that your explanations should help any reader to understand what your issue is. A short line of "what if it is inline" added to a thread that was in the first place not only ambiguous and unclear but equally short handed, really only can increase confusion but not make anyone understand what the actual problem is from the two dozen that many might consider possible.

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Hi rolfk,

 


But when you post a problem/question here, you have to always assume that we know absolutely nothing about your problem and that your explanations should help any reader to understand what your issue is. A short line of "what if it is inline" added to a thread that was in the first place not only ambiguous and unclear but equally short handed, really only can increase confusion but not make anyone understand what the actual problem is from the two dozen that many might consider possible.

I already accepted my mistake of confusing RTSLVU and apologized to him as my question was just to him. My aim was not create confusion resulting into a snowball effect. I will make sure that if I have to raise additional question about an OP's problem. I will make it detailed. 

 

Peace!

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@N_743 wrote:

Hi Johntrich,

 

You got the wrong guy. You will have to say this to the person in the first post, jeet4230.


Have you gone through any of the LabVIEW tutorials? 


Yes, I have and completed core 1,2,3, Advanced Architecture, RT and FPGA.


My apologies. I did not notice that you were not the OP and misunderstood the purpose since your question seemed to be adding details to the OPs post. I am sure that the language gap that you mentioned earlier contributed. Thanks for pointing out my error.

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