complex data acquiring/generating

[the_intern]

I need to design an ISA Bus VI in following manner:

- All digital lines are based upon same clock (8MHz) (Ni 6289)

- 4 more lines happening at the same time, one after another. (Ni 6289)

- 16 address lines (Ni 6289)

- 16 data lines (Ni 6541)

- Display CLK, those 4 lines, address and data lines on the same graph

I will provide more info if neccesary.

Thanks

[Gabi1]

lots of duplicate posts !!

here

here

here

and more as i pass trough...

you need first to explicitely depict what you want and where are you stuck, then come for questions. read carefully all the answers in the other posts, there is already quite a bit of info in them. if you still have problems, please keep one single thread, so all people helping could follow one each other.