confused about DMA channels available

[ghattas.akkad]

hello i have the RIO-PCI7830R fpga pci card

in the card details it says that i have 3 DMA channels available

i want to know how do i count these channels when working like:

i can only have 3 FIFOs working simultaniously : lets say i have a program that requires 3 inputs and 3 outputs can i initialize 6 FIFOs and use them but only 3 at once

or i can only have 3 FIFOs in total that means i can only have 2 inputs and 1 output total of 3

DMA settings of the pci card

   DMA:
      Number of DMA Channels: 3
      Multi-Element Access on Target: Not supported
      Peer-to-Peer Streaming: Not supported

[srm@viewpointusa.com]

three total.

you can use them for different purposes at different times but that will be up to your code to implement that level of sharing.

[ghattas.akkad]

so i cant really have 3 fifo inputs and 3 fifo outputs

it should be 2 inputs and  1 output

thank you

[Simon_T]

Hi,

You can have as many "inputs" and "outputs" to a DMA FIFO as you want, but you are limited to 3 DMA channels - overly simplified, this is the "memory behind the FIFO", and you can have a total of 3.

You can find many great examples and tutorials online about using DMA in LabVIEW, I recommend starting with this:

Transferring Data between Devices or Structures Using FIFOs (FPGA Module)

Best Regards,

T Simon

[ghattas.akkad]

thank you

just one more question please

if i have my design simulated on xilinx and reslted in 2.708ns clock

how can i know how much the DMA protocol implementation will overhead on the clock

what is the timing restrictions on the DMA?

will it cut my speed and result in a slower clock or does the DMA work on fast clock ?

[Simon_T]

Hi,

May I recommend our LabVIEW FPGA Training courses.

The DMA FIFO Node in LabVIEW FPGA will "wait" for data to become available.

You can add determinism by using the "Timeout" input of the FIFO Node. You can use the "error out", "Timed out?" and "Elements remaining" nodes for control.

If you set this "Timeout" to 0, there will be no "waiting" included, now you can create a benchmark application and run it on your actual hardware to figure out the exact, fastest possible speed on your device (as they will be different depending on the FPGA type - and we do not have this data readily available.)

You may also want to read through this article:

Best Practices for DMA Applications (FPGA Module)

Best Regards,

T Simon

[ghattas.akkad]

ok thank you 😄 ill go through all the articles

id love to take the training but they are a bit expensive where each core is about 1000$ ill stick for reading examples and understanding them for now 😄