construct a closed loop control VI using Control & Simulation Loop

[old_boy]

Dear all

I want to use a mean value of 40000 samples as a feedback signal to construct a PID controller and the sampling rate is 100kHz. That means I will acquire 40000 samples (0.4s) in each loop, and the difference between the mean value of these samples and the set point is used as the input of the pid controller, the output of the pid controller is used as the amplitude of a sinewave signal. The example VI is in the attachment. For convenience, I have set the gain in the controller to 0, so you can treat tihs VI as a synchronized AI and AO.

Questions:

(1) Each time I run this VI, it will stop after few milliseconds, and the "Simulation Parameters Function" indicates "finished late". I don't konw where is wrong. The step size is 0.4s which is equal to the data collection time for each loop.

(2) When I remove the "Simulation Parameters Function" module, the VI runs continously. But when the amplitude of the sinewave of the output signal changes, there is a small gap (few milliseconds) between the two different signal. How can I remove this gap?

Thanks for you attention!

Sincerely yours

Mr. Wu 

[Che_T.]

Hi Mr Wu,

Thanks for the detailed post

(1) It looks like the problem is that too much processing is done within each iteration of the loop, causing it to finish later than your intended rate.  Trying to achieve such a high rate will be very difficult to perform in software.  So, that's why you see the "Finished Late" in the bundle.  For your CPU to keep up, you'll have to lower the rate significantly.  For such a high rate, I'd recommend using a hardware solution such as LV FPGA.

(2) By removign the "Simulation Parameters" function, you're allowing the Control & Simulation loop to continue running even if it finishes late.  So, now you're getting valid data, but we're still running late.  So, your data is likely to drift over time because the CPU cannot keep up with the rate that you intend it to.

I hope this helps!  For more info, please see this KB

http://digital.ni.com/public.nsf/allkb/CFD12F7248B4D9D78625752700388A74

[old_boy]

Hi,Che T.

Recently I have disabled the "Enable Synchronized Timing" option in the "Configure Simulation Parameters Dialog Box". The VI does not indicate finished late anymore. I think maybe my designed VI is changed from a PID controller example, which is one sample input one sample output in each loop, "Enable Synchronized Timing" is not suitable for my case, so I can disable this option. Am I right?

Thanks for your help!

Mr. Wu