delay needed between two timed loop structures

[cds195]

Hi,

I need to generate a CLOCK and DATA signal for putting into a shift register (hardware, not labview). However, there needs to be a delay between the first bit of data being generated on the DIO line and the first clock cycle being generated on another DIO line. How do I put a "delay before starting" onto the CLOCK timed loop structure? FYI, this is in labview FPGA module. The two loop structures will both be inside a for loop.

Many thanks,

Craig.

[GrahamG]

Hi Craig

If you are using a timed loop structure then I would look into the offset function.

Offset / Phase—Specifies the starting time or phase for the iteration of the structure. You can use this option to synchronize structures or align their phases. For example, you can configure two Timed Loops to use the same timing source instance by specifying the same name in Source name. In one Timed Loop, you can enter a value of 0 in Offset / Phase and in the other Timed Loop enter a value of 100. The Timed Loops execute at their respective periods, but 100 timing units separate their execution.

I'm not sure if this is exactly what you want but if you could attach your code then I will take a look and then have a better Idea of your aims. What have you got so far?

best regards

[cds195]

Hi Graham,

thanks for the reply. I cannot find an option anywhere to change the phase/offset. If I double click on the timed loop structure, I only have the option of selecting which clock to use (FPGA or FPGA-derived clock). Unfortunately I cannot import an image of the wiring diagram, but I suspect the timed loop is different to the timed loop in FPGA Module??

On a slightly different note, do you know of a straightforward way to get a square wave generated from an FPGA-derived clock (apart from doing a timed loop with a NOT gate inside)?

Thanks,

Craig.

[Prashant M]

Hi Craig,

 

Thanks for your message.   I have had a look at your problem and I think that a possible solution is to use a flat sequence structure.   The first sequence should contain a wait function inside a case structure linked to a first call function and the timed loop structure should be in the second sequence.  Using this you should be able to set the delay.  I have written an example VI for you showing this set up.  I have attached this example VI to this message.  I hope this helps.

With regards to the square wave, there are some example VI’s if you go to Help >> Find Examples >>  and you search for “square wave” you should be able to see several projects, in particular one called "Square Wave Generator cRIO" which may be useful.

I hope this helps with your application.

Kind regards,

Prashant M
Applications Engineer
NI UK & Ireland