downconverter/digitizer will just not PLL to the backplane!

[mimomar]

Hey all,

I am trying to implement a 2 by 2 mimo wireless communication system. I currently have set up, 2 transmit and 2 receive chains. ie the set up on my pxi has :

Receiver 1:  NI 5600(downconverter) and 5620(digitizer) in slots 2 to 5 (the 5600 will drive the backplane clock)

Transmitter 1: NI 5610(upconverter) and 5421(AWG) in slots 6 to 8

Transmitter 1: NI 5610 and 5421 in slots 9 to 11

Receiver 1:  NI 5600 and 5620 in slots 12 to 15

Now i have sucessfully implemented a 2-by-1 system, in that system i use the first downconverter to drive the backplane clock and it work and the transmitters succesfully PLL on it and everything is fine.

 I'm trying now to add another receive chain using the hardware in slots 12-15. I need the two receivers to be synched so I need this receiver to PLL to the backplane also.

First experiment which i thought should work, was trying to run another instance of my receiver vi (which is working). but now instead of driving the backplane clock i set the 5660_configure_ref_clock.vi's clock source to the PXI clock. I run the inital receiver to start driving the clock, then the secondary receiver but i keep getting the error that the device could not pll to the clock. Although if I run the transmitter, they PLL to it just fine.

So why is it that just the receive chain in slots 12-15 canot synch into that clock??? 

[mimomar]

hey all,

is this not the right forum for this question? should i post it in one of the device forums, please advise... i'm still having alot of trouble with this

[Bueller]

Hi Mimomar,

Thank you for posting on the discussion forums.

Before answering your question, I have few things that I need to mention. I believe you are trying to implement a 2 by 2 Mimo wireless communication.

In order to have a MIMO system, you need to ensure phase coherency among the different modules you are using.

The 5600 has it's own LO that can not be shared with any other module as for the 5610. When you PLL the clocks of the baseband modules ( Digitizers and AWGs) you will ensure that these module are locked to the same clock, but what about the 5610 and 5600???

Each of those are still using their own LOs that can not be shared, and therefore you can not guarantee a fixed phase difference between the different VSG and VSA between different runs. ( If the phase difference is fixed, you can account for that in your measurement).

However, if you plan to go on the current setup, a more accurate way to ensure that all baseband components are synchronized, you can use TCLK. To do so you need to extract the AWG session from the RFSG session and the scope session for the RFSA session and TCLK them together.( even with this setup the upconverters and downconverters will have two diffferent LOs).

Finally, I would like to mention that if you want to have a real MIMO system, you might want to consider to upgrade to the new 6.6 GHz RF platforms ( 5663 & 5673) . These modules use the 5611 as an upconverter and the 5601 as a downconverter. With these modules you can share the LO for the analysers on one end and the LO of the generators on the other side.

Best regards,

Faris A

[mimomar]

Hey,

Thanks for the reply. I am aware that they use their oscillator, and your definitely right that it is an issue for proper MIMO system. Given that i want to implement 6x6 MIMO (actually 3 2x2 synchronized mimo links) I dont think we will upgrade to the new RF modules now, however I think we will consider it. So we cant synch the RF signals, but we can synch the IF. 2x1 works almost perfectly right now, the phase coherence has not given MUCH problems so far, and for my app, as long as for some runs I get a "proper" link then i'm fine.

 So my question, in its simplest form is, why does the 5660 not lock into the backplane clock wihen I tell it via the Configure Ref Clock.vi or ni Tuner vi's...

[Steve_B]

Hi mimomar,

You may be running into an issue where the PLL circuitry is having trouble locking due to noise coupling into the lines. I would recommend that you try connecting your reference externally to the FREQ REF IN connector. You will be able to lock to this signal in the same manner that you lock to the backplane clock. You should see improved signal integrity for the clock using this method. You can also try testing this 5600 in another slot to see if you can get it to lock elsewhere.

Steve