I am trying to achieve a loop rate of 2.5 kHz on the the real-time vi. While the inner current control loop on the FPGA is running at a loop rate of 8 kHz.
- I have used a timed loop and instead of merged signal function, I have used a cluster block for the charting. This has led me to achieve the loop rate of 2.5 kHz consistently. I am using a timed loop to do the same. I have attached my code below. Can you go through my code once, and if possible can you suggest how I can optimize it further?
- When I replace the timed loop with a while loop, and benchmark my code, I can observe a lot of jitter being present in the code. I have used the benchmarking project available in one of the LABVIEW examples to provide a timing analysis of my code. The amount of jitter present in some iterations is extremely high. Can you please shed light on why this is the case?
