fpga VI - hysteresis logic and count

[SJ BSB]

Hello,

I tried to implement hysteresis logic and count the number of times when the signal is cross above the threshold. But the counter keeps incrementing continuously.

SJ

[Kosta]

From a methodology standpoint, I would recommend testing the algorithm on the computer before trying to put it in the FPGA.  You can create a test case by supplying a set of inputs and expected outputs, then test your algorithm against these values you computed yourself.  I am not sure what your definition of hysteresis is, especially when it comes to the start-up conditions.

I am attaching a couple of VIs to illustrate this method.  My definition of hysteresis may or may not match yours, but I hope that you find the approach helpful.

[SJ BSB]

Sorry, I have solved by bringing the feedback also as in input terminal and used in my mail VI. Before implementing in my FPGA vi I have tested in PC and in RT. I faced problem when implementing in FPGA. The modified VI and picture are attached.

Thank you,

SJ