fpga app stop problem

[Damir]

Any idea why this vi, deployed to host PC, can't be stoped using stop control? It must be killed with task manager.

Problem arised with ver. 8.6. I have foour systems with diferent cRIO hardware, but everywhere the same problem.

I don't want to use Close FPGA Vi Reference, because it resets my output states which I cannot afford. I/O count is >200.

 The Vi is simplified down to the core of a problem.

 What can I do to speed up selection of a I/O point in Read/Write control? When I need 50 or more nonconsecutive points,

it's zzzzzzzzz....... sleepy slow.

Thanks in advance

[CMal]

Damir,

Do you see the same problem if you add a small wait to the while loop?  In your example, LabVIEW will run the loop as fast as possible, taking 100% of your CPU's resources.  This is probably why the front panel becomes unresponsive.

Chris M 

[Damir]

Dear Chris,

like I sad, I simplified Vi to the base of problem. In actual Vi there is a waiting time. I've had that problem on cFP and

vi with a lot of polling inputs(loops), and one was without waiting. Just before using a hammer, I spoted trouble... 

This behaviour began after upgrading 8.5.1 to 8.6. I'll try upgrade to 2009 for future use, but I have 4 systems running with this trouble.

[RavensFan]

Then add a wait to the one loop that is missing it and see if it improves.

[Damir]

Chris,

my loop has wait time, front panel is responsive, quit labview function closes front panel, but the coresponding process is still runnung in task manager and windows toolbar. If I use Close FPGA Vi Reference, application closes normaly, but I reset outputs on cRIO, what I don't want. Let me rephrase question. How can I close FPGA reference without reseting FPGA in LV 8.6? 

[e2m0i0l7 · Accepted solution]

Hello Damir,

In order to close the FPGA Refference, but not reset the FPGA, right click on the Close FPGA Refference VI and choose close, instead of close and reset, which is the default setting.

Please reply if it works for your application,

Emil

[Damir]

Chris,

I'm not able to try it right now, but I know that works OK if I explicitly close reference. So I'll consider case solved!

Thanks very much. It was black spot on very nicely vorking system. 🙂

Furthermore, in testing period I often riched max number of open references to FPGA... 

Damir

[Damir]

Sorry, Emil,

the last post was adressed to you. Thanks again