fpga array size (why 32 elements?)

[Dan_Acres]

I'm creating an FPGA to do some fairly simple but labour intensive (read many repititions) array calculations.

I'm attempting to pipeline it to make the process run a little faster, but am wondering what I should do with my arrays.

I have replaced all but one with memory writes/reads as they are only read after the initial writing.

There is however a 78 element I16 array left over which must be fully populated and read each loop.

I've pipelined writing and reading from the array to speed up the VI a little and tried to parrallelise the process as much as possible (writes 6 chunks of 13 elements at a time, reads 6 chunks of 13 elements at a time).

The pipelining restricts me from using memory reads/writes as these would require sequential reads/writes, as far as I understand.

I've read that you're 'not supposed' to use arrays greater than 32 elements, but I've not been able to find any justification/explanation.

Is that hearsay or would I benefit from splitting the 78 element array into 3 32 element arrays? 

The code is small aside from the arrays - it is performing a very simple task but loop rate is important.

Thanks in advance

Dan

[Dominic.Walker]

Hey Dan,

Take a look at this knowledge base article.  It should explain why large arrays are a bad idea within FPGA code.

Have a read though, and look at some of the links as well.  If you have any questions after reading it - let me know. 

Kind regards,

[Dan_Acres]

Thanks for that Dominic - it has answered most of my questions.

It seems as though the keeping array sizes below '32 elements' is hearsay then.

The only metric that matters is that for arrays where the total size (no of elements * bit depth) is > 32 bits then double buffering is required (eg 2 flip-flops per bit)

I theory it is more economical to split a 16bit array up into 2 element, 32 bit 'chunks', but in practice this would make the code very complex!

Does that only apply to arrays/clusters that are visible on the front panel of the FPGA?

I had thought that clusters without front panel indicators were 'free' and entirely virtual.

On a side note, could you explain how block memory access from inside SCTLs works?

I can't make sense of the fact that it takes ~25 ticks to access a 16bit value in a non timed loop, but a timed loop can access one every tick.

The help said something about the result not being valid for 2 loops - does this mean the result needs to be fed into a shift register to be read from on the next loop?

Thanks for the help

Dan