fpga bitfile generated and timing violations

[fengels]

Hi all,

 how is it possible that a bitfile is generated when there are timing violations. Is this bitfile still runnable and what problems can occure when you run it.

 I use labview 8.5.1

Regards

Frank

Message Edited by fengels on 04-28-2008 08:47 AM

[Wiebe@CARYA]

Not sure if a bitfile is generated when there are timing violations. It
might always be generated, or perhaps an old bit file is only deleted if the
new one is create. My guess would be it won't function at all.

Regards,

Wiebe.

[fengels]

Wiebe,

 Thanks, Something stange happend here, perhaps the old bit file has been run.

Cannot reproduce it, so problem is "solved" 😉

regards

Frank