fpga: dynamic mode vs type def for FPGA ref

[jyang72211]

What are the differences for dynamic mode and type def for FPGA referenece?  When should I use which?  Is there a scenerio when I should use neither?

[jyang72211]

Can anyone help me with this?

[T-REX$]

Hey jyang,

The answer is really that you should always use Dynamic Mode. I still create a type-def of the interface for passing in and out of subVIs, but I haven't found a need to bind the Open FPGA Reference to a type def anymore.

[jyang72211]

What do you mean by you are using Dynamic Mode, but you are still using type-def for the reference?  Once you select dynamic mode, the binding to type-def optoin is greyed out, so how do you do that?  I always understand that the main purpose of creating a type-def for FPGA reference is for using the reference in a subvi.  Is dynamic mode doing the same thing?  

[T-REX$]

So, you can still create a Type Def of a Dynamic Interface Refnum... That sounds confusing I know. Basically, my design flow is generally as follows:

1. Develop initial FPGA code.
2. Create a Control or Type Def with the FPGA Interface control configured for my FPGA VI.
3. Develop my host, and use the Type Def in all of my subVIs.
4. If I need to edit my FPGA code, now I only have to update the control in the typedef to propagate my interface changes to all of my subVIs

Basically, every project I do has a FPGA Reference typedef for use in my host VI.

Attached, you can find a (incomplete) sample project of mine that does this.

[jyang72211]

To bind FPGA reference to type definition will allow me to update the control in typedef to propagate the changes to all subVIs, so what is the additional benefit of using dynamic mode?  Also, are there others beneifts for binding FPGA reference to type defiinition?

[T-REX$]

The biggest advantage of Dynamic Mode is the ability to create reusable host interface code. In static mode, the reference wire is target dependant. Even if the FPGA VIs have exactly the same FIFOs, Controls, and Indicators, a new project will require rewriting your host interface code.

In dynamic mode, multiple bitfiles can share a common FPGA reference as long as they have the same named set of Controls, Indicators, and FIFOs. You can specify which bitfile you want to use at run-time, and you can specify the interface at run-time. If you want your host VI to support multiple bitfiles (even for different targets) then you have to use Dynamic Mode.

In addition to all this, I have found Dynamic Mode to be more stable and behave more as I would expect. So my recommendation to everyone is to use Dynamic Mode for everything always.

[jyang72211]

If the two different FPGA VIs have different controls, indicators, and FIFOs, I can't reuse the host VI with dynamic mode, correct?

[David-n-MO]

August 2022 and waiting for an answer...

[rolfk]

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@jyang72211 wrote:

If the two different FPGA VIs have different controls, indicators, and FIFOs, I can't reuse the host VI with dynamic mode, correct?

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Not without relinking the FPGA refnums to the new FPGA interface (which is a collection of all front panel controls, FIFOs, etc).

The type in the FPGA refnum determines what items you can select in the according property nodes and methods.

And this is where the typedef comes in handy. When you link your FPGA Open to a new bitfile, the refnum in dynamic mode adapts to the new interface definition (but is now incompatible to any refnum control in the rest of your VIs). By having that refnum a typedef, you can update the typedef with the new interface (I usually do a create refnum on the output of the FPGA Open and then copy that on the front panel to the clipboard and go into the typedef and replace the one there with the new from the clipboard). Et voila all your VIs now use this new FPGA interface (and will break when they referred to a register (FP control) or FIFO that doesn't exist anymore or you have forgotten to use the typedef in some place).