fpga multiple instances of a single LUT

[QuanTom]

Hi,

I would like to implement multiple instances of a single Look-Up Table (LUT) into a single timed loop. Is there a way to use a single LUT called with different parameters, instead of declaring multiple LUTs called with single parameters. The LUTs are simple Cosine curves that I would like to make as big as possible (~2^14), but I am currently saturating the FPGA memory (PXI-7852R) when using 4 instances.

Regards,

Thomas

[JLewis]

Hi Thomas,

There is no way to reconfigure the LUT 1D at run-time, so you need a separate LUT for each curve. The FPGA architecture doesn't allow swapping out memory elements; the only way to accomplish this would be to use Memory Read/Write methods and write the new data in one element at a time from the host computer.

There are several techniques to efficiently re-use smaller cosine tables with addressing and interpolation tricks. Direct Digital Synthesis (DDS) is a method of stepping through the same table at different rates, and is how the Sine Wave Generator works.

[QuanTom]

Hi,

Thanks for your reply. Note that I don't want to rewrite the LUTs, but only read them (each contain the same cosine over the same length). That's why I feel like wasting memory when implementing several instances. Also interpolation is out of question as I am using them in single-cycle loops.

[JLewis]

I see. I thought you were saying that each LUT had different contents. The "different parameters" would just be the addresses, I guess?

This is a resource sharing problem, which is a do-it-yourself proposition in the SCTL. Interpolation is not out of the question, but you would have to implement it explicitly outside of the LUT. The main problem is a bottleneck in hardware at the address port--you can only get one element out at a time, so in your case, the LUT code would have to run 4 times as fast as your parallel data rate. If you're in a recent LabVIEW version, one possibility is to use a Memory Read configured for dual port reads (look at the Interfaces section of the Memory property page). That will give you a read-only memory where you can read 2 addresses in parallel. You can either use those 2 addresses to implement interpolation on a single channel, or to execute 2 channel reads in parallel.