fpga must recompile

[longbow]

I have a compact rio project with an FPGA target.

I compile and run an FPGA file without issues.

When using the "Open FPGA VI Reference.vi", I can specify the VI or the build definition.

Either way returns an error :

Error -61017 occurred at Open FPGA VI Reference in rt2_xzec-iii-9073-d8va16t8.vi

Possible reason(s):

LabVIEW FPGA:  You must recompile the VI for the selected target.

I have tried the following :

1. Specify a different VI, then OK, then specify the actually desired VI.

2. Switch between specifying the VI and the build definition.

3. Delete the "Open FPGA VI Reference.vi" and put it on the block diagram again.

4. Rebuild the FPGA code (it says that it is up to date)

What else can I do?

[longbow]

More details :

1. The VI was created in LabView 2012, but I'm now using LabView 2013

2. I've tried deleting the build specification for the VI - same problem

3. I've renamed the vi, and recompiled - same problem

4. I've created a new vi, and copied the logic across from the old 2012 VI to the new vi - same problem

5. I've created a new real-time app with just the "Open FPGA VI Reference" - same problem

6. I've formatted the CRio 9073, and put NI-RIO 13.0 on it.

7. My patches and updates of LabView are up to date.

8. I'm not using object oriented programming.

9. The RT vi is open when the FPGA vi compiles

10. The FPGA VI is open when the RT runs

11. I am not using any FPGA IP blocks

[Matthew-B]

Hi longbow,

Thanks for all the details! I found a KnowledgeBase article pertaining to the error you are seeing, but the issue had been fixed back in LabVIEW FPGA 8.0.

Could you check the signature of the FPGA bitfile so we can see if there is possibly a mismatch? If you right-click on the build specification for your project, choose "Check Signature". If there is a mismatch, I've found some instances where deleting the existing bitfiles and recompiling has helped.

Regards,

[longbow]

This is definitely just the result of upgrading to LV2013.

No sorry to disappoint - the signatures match "The bitfile is up to date with the build specification." is the result of checking the signtature.

I've since tried :

1. create a new project, create a new crio & fpga target matching the old one, and imported the vi and libraries - once again FPGA runs by itself, but "Open FPGA VI Reference" returns the error.

2. also tried compiling it on a different computer (one of the NI application engineers at our local NI branch) - same result

So far my only workaround is to specify the bitfile instead of the VI - not ideal, but it works.

[Matthew-B]

Hi longbow,

Do you have any SubVIs in your top-level FPGA? If so, are any of them stored outside of the FPGA context in your project?

Regards,

[longbow]

Yes I use subvi's - they are in an library stored in the FPGA context, but I have several different CRio targets in the same project which all use that library.

[Matthew-B]

Hi longbow,

Are the cRIO targets the same? The bitfile that is generated is specific for a target, but it can be used across targets that are the same (i.e. a bitfile compiled for a cRIO-9073 can be used on other cRIO-9073s, but it cannot be used on a cRIO-9075).

Would you also be able to provide a screenshot of your LabVIEW project so I can see how it is set up?

Best Regards,

[longbow]

No, the compact RIO's are different.

I have a library of utility subvi's like read a 9401 card in slot 1, and simliar types of items, but the top-level VI is custom per target, and the RT for that target uses its specifically compiled FPGA.

The fact that the FPGA code runs on the target successfully proves this.

If I refer to the FPGA VI by its bitfile, I am able to execute the RT from the development evironment, but it does not execute at startup.

If I diagram disable the FPGA Open, then the code does execute at startup.

I'm seriously at the point of downgrading to LabView 2012 if NI cannot solve this issue for me soon.

I've given the local NI Application Engineer an instruction to internally escalate this problem, as it making us look like real idiots to our customers.

[longbow]

I can create a new LV 2013 project, with a basic FPGA app, compile it an refer it to via its *.vi name in the FPGA Open, and it executes fine via both dev environment and execute on startup.

[longbow]

Screenshot of project attached.

Btw - while I don't wish to release my source on the forums, I could arrange for NI techies to get it.

I suspect that our local AE will be uploading it when he escalates.