fpga node not reading in rt system

[user50]

I have a fpga read node in my cRIO software that is very flaky.  What I mean is that usually it reads the variables, but then I go into the vi and change the code that has nothing to do with reading the FPGA, save it, and now the the fpga node returns all 0's.  I can open and run the FPGA vi, and the data is being updated and non-zero.  Other FPGA read/writes in the crio program are fine.  It's just one VI that you modify, and it breaks but no error's are posted.  Just returns incorrect data like nothing is wrong.   Usually, I have to delete the FPGA reference and FPGA read node in order for it to work again.  I have no idea what is causing this.  Has anyone else had a problem reading an FPGA node?

[0utlaw]

Hello Finjo,

I've seen (somewhat) similar behavior in VIs that use uninitialized shift registers to store FPGA references (think functional global variable for DMA FIFOs); I'd have to look at your code to be sure, but in that case I was seeing that methods would error out due to improper linking if the initialize was modified but invoke methods were not re-linked.  This may be happening in your code, but the errors are getting swallowed due to your error handling and default values are returned from the FIFO read.

*If* this is the problem, you should be able to fix it by copying the source of the FPGA reference (Control or FPGA init) outside of your loop to "initialize" the shift register- this will re-link invoke nodes that use this reference within the primary loop. Once you've done this in the development environment, you should be able to delete the reference source.  Posting your code or a piece of it that reproduces this so we can see your architecture would be very helpful though.

Regards,