fpga- optimum PWM generation

[Arnie1]

Thanks for the reply. I'll try to post pictures as JPEG in future.

I thought I read somewhere that the SCTL will run as fast as the internal code permits. If that's not the case, then for some reason, my SCTL PWM loop is running in two cycles with a maximum output frequency of half of what it should be if it were based on 40MHz?

[nathand]

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Arnie1 wrote:

Thanks for the reply. I'll try to post pictures as JPEG in future.

I thought I read somewhere that the SCTL will run as fast as the internal code permits. If that's not the case, then for some reason, my SCTL PWM loop is running in two cycles with a maximum output frequency of half of what it should be if it were based on 40MHz?

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Here is the Single-Cycle Timed Loop FAQ.  I don't think I understand your question: you said your loop executes two cycles with half the frequency you expect; wouldn't that mean that a single execution takes exactly what you'd expect?  Also, I don't know what the specifications are for the digital output module you're using, but it's possible that your loop runs faster than the digital output is capable of updating.

[Arnie1]

I meant that it seems to be taking two clock cycles to execute in the SCTL. However, that is still much better than the minumum of 6 clock cycles in the standard while-loop that it replaced.

I just want to be sure that the use of SCTL will be robust in the application, but I'll read the FAQ's you indicated.

Thanks.

[Wiebe@CARYA]

"Arnie1" <x@no.email> wrote in message
news:1226932809376-810042@exchange.ni.com...
> I thought I read somewhere that the SCTL will run as fast as the internal
> code permits.

That is not entirely accurate A SCTL will run at the FPGA frequency (40 MHz)
IF the internal code permits that. It won't go faster, as your description
implies. If the internal code doesn't permit that, it won't run at all,
since it won't compile. So it will run at 40 MHz or not at all...

Regards,

Wiebe.

[Arnie1]

OK, that's a good clarification. In my case it's running slower than I expected (= 2 cycles, instead of 1). But it does compile OK, so perhaps I have an error somewhere else, not related to the SCTL, that is causing the output frequency to be 1/2 of what it should be.

[Arnie1]

Siege-X,

I hadn't noticed this the first time I tried your example PWM software, but I don't seem to be able to get the time-offsets to work on my system. I even tried using fixed values. Is there some set-up I need to do first.?

Another thing, I notice that you have used shift registers in the eight individula loops to buffer the output. I guess this is done primarly to deskey any possible timing differences between the 8 outputs, although it does add once clock-cycle delay? Also, since the 8-outputs are fed into anothe loop with its own shift register for the digital outputs, are the 8 individual output shift registers really necessary?

My initial version was to put the code for the 8 outputs in to just one timed loop, with a count offset for each PWM count, rather than individaul loop-time offests. This results in more compact code, but are there any possible disadvantages to this?

Thanks

A.

[Vadivelu N]

Hi i am vadivelu here. i dont know how to create a new query. as my quey is related to this i am just continuing with this.

I have done pwm output using PXI7833R and its giving the output frquency as very low(if i designed 10khz its giving 3 to 4hz). I think the problem is here the increment and and checking should be a atomic operation but its not working as a atomic operation.

Please tell me a good idea to design a counter and check it with the High and low ticks.......

My code is attached here.....

[ThomasC]

Hi Vadivelu,

I am unsure of your exact problem but suggest that it might help you to take a look at one of the examples within LabVIEW.  Please open the Example Finder and select 'Hardwear input and output >> R Series >> FPGA Fundamentals >> PWM Output >> PWM Out, Simple - R Series.lvproj'.

If this doesn't help you resolve the problem please feel free to ask any further questions.

Regards,

Thomas Clark

[M_Silva]

Hello guys,

i am Mário and i'm working with a cRIO trying to control a IGBT bridge, i've tried some PWM generations from examples that o saw but when i took a look at the ones you are discussing here i found it more interesting and they really work fine.

Unfortunately i still have a problem, every time i run my host code from the very first time the chanel 0 (zero) starts at high state befora i click START, and that's not desirable..when i click start the PWM generation works fine and when i click STOP they go to the low state as i wish. I tried to use local variables to initiate them at low state but i get an error say that the local variables were recieving outputs from more than one control.

If some one can help me fixe this or give an idea to work this out i would be very greatfull.(i'll attach the code i'm using)

Thanks

Mário Silva

[nathand]

I don't see anything that would explain the specific problem you're having - it's only channel 0 that starts high, and channel 1 starts low?  Is there a setting somewhere in the project or module configuration for the startup state of the outputs?

That said, your code is more complicated than it needs to be.  The local variable for Stop PWM wired to the inside of the shift register isn't doing anything, it will always be false.  You don't need the while loop around the timed while loop, one is sufficient.  You could handle the Start PWM condition inside the same loop that writes the outputs.  Use a shift register to determine if the Start PWM button has been pushed (use the shift register OR'd with the button value), then AND that value with the value being written to the outputs so that you'll get a false (low) value when PWM generation isn't running.  Clear that shift register when the Stop PWM button is pressed.