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fpga single-cycle timed loop subvi that retains indicator values between runs

Hello folks,

 

Is it possible to create a subvi for use in an fpga single-cycle timed loop that has persistent indicator values between runs?

 

I know this cannot be done using uninitialized shift registers because while loops are not permitted inside SCTLs.

I know I can feed the value of the indicator out of the subvi and to a shift register on the SCTL, but this is creating "messy" code that is becoming quite challenging to maintain.

 

Is there a better way?

 

Best Regards,

Chris 

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Chassan,

 

Here are three methods you could try. A feedback node acts essentially as a shift register, thus giving you the performance you want, but with much less wiring. When you run this VI on the PC, all three of the LED's blink at the same time. I haven't tested it on an FPGA to see if it will compile, but I don't see why it wouldn't.

 

1.) SubVI with Feedback Node Setup

2.) Feedback Node Setup

3.) Shift Register

 

Timed_Loop.PNG

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Ben Sisney
FlexRIO V&V Engineer
National Instruments
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