fpga vi fails to be triggered from RTSI line

[graduate student 44]

i'm having several pxi-4472 cards collecting data and a seperate pxi-7831r card taking timestamps on the same chasis. i made the fpga vi on pxi-7831r listen to RTSI0 bus, also on which the master 4472 card triggers the slave cards to collect data. the synch and stream works fine but somehow fpga vi refuses to be triggered by RTSI0 bus. i then switched digital input from PXI/TRIG0 to every other options, nothing seems to work! i'm attaching related files. is there any config trick i have to do?

[Christian_L]

I looked at your VI yesterday and it looked fine to me.

Can you please describe your complete system setup in detail. What controller and chassis are you using? In what slots are each of the cards located. The 18-slot chassis needs some special configuration for routing the backplane signals.

How are you configuring the 4472 to share the scan clock signal on RTSI0? In your VI I only see the AI Start Trigger being routed to RTSI1 and the board clock to the Star Trigger lines. The start trigger will only have a single pulse at the beginning of the acquisition which would not give the expected result in your FPGA VI.

Christian L

[Christian_L]

I just noticed that indeed you are using the 18-slot PXI-1006 chassis. This will require special configuration to route the RTSI trigger signals. Please review the information in this article and make the necessary configuration.

Christian L"

[graduate student 44]

thanks! hi, i just realized that "AI start trigger" only triggers once, that makes sense then, cuz i've kept getting one trigger for a entire data acq session. i'm trying to route "AI Convert" as the source signal to "RTSI0", but am not sure if this is the right thing to do. i assume "AI Convert" output a pulse (in my case to RTSI0) whenever a data sample is taken?

[Christian_L]

For the 4472, I don't know off hand which is the correct signal name, but try 'AI Convert', 'AI Scan Start' and 'SCANCLK'.

Christian L