fpga vi's

[Mudda]

Hello,

             I am new to real time and also to FPGA. I am using Analog input, Digital Input and also Digital Output modules. what is the best way to do the data acquisition? is it by creating a seperate VI for each IO module or shall I create 3 threads in one VI?

thanks,

mudda.

[Steven_T]

Hello Mudda,

Assuming that you are using both LabVIEW FPGA and LabVIEW Real-Time as the controller, then you have several options.  With LabVIEW FPGA you are programming the hardware of an FPGA, so parallel loops are actually running in true parallel in LabVIEW FPGA.  This means that you could be getting data from each of your modules at the same time in separate loops.  However, the Real-Time vi that is receiving the data is not truely parallel, but it is deterministic.  This means that you can expect more precise performance from the VI.  It does not make much difference if you are acquiring the data from the FPGA in the same loop or in different loops for each module.

Here is a link to a class/tutorial that has an introduction and advanced topics like how to share the data between the Real-Time VI and the FPGA VI. 

I hope this helps.

Steven T.

[Steven_T]

Link: [broken link removed]
 

[Mudda]

Hi Steve,

                Thanks for the reply. It was helpful to me. I have another question, I am reading the input from 4 channels. What is the best way to trasfer the information from FPGA VI to the Host VI. In my application the VI on the FPGA will be running 5 or 6 times faster than the Host VI. I was thinking of creating a DMA FIFO and put each channel data into the FIFO one after the other and and seperate them in the Host VI by taking every 4th element in the FIFO. Is this a good way to handle the data between FPGA VI and the Host VI for multiple channels data acquisition? I dont have my hardware yet to try out these methods. Is there any way I can simulate the hardware?

Thanks,

Mudda.

[Steven_T]

Mudda,

I am glad that the information was helpful for you.  Your current ideas about transferring data from the FPGA VI to the Host VI are exactly what we recommend.  There is a developer zone document that even has your same application.  They are reading from 4 AI channels and then putting them into the FIFO.  Except it looks like they put a single element at a time.  Since your FPGA VI will be running faster, make sure that there will be periodic breaks in the data or you will fill the FIFO and receive and error.

https://forums.ni.com/t5/Example-Code/Use-DMA-FIFOs-to-send-data-to-and-from-an-FPGA-target/ta-p/352...

Since you mentioned FIFOs, you are using LabVIEW 8.0 and LabVIEW FPGA 8.0.  You can create your project and then create new hardware (right click the project and select new->targets and devices).  If you select new target or device, then you do not need the hardware.  After adding your FPGA, you can right click the FPGA and select properties.  You can select to turn the emulator on so that you can do your tests without the hardware.  I hope this helps you. 

Steven T.

[Mudda]

Thanks for your information.

Mudda