12-14-2009 10:59 AM
Boolean arrays and fixed point numbers are not supported by the logical operators in single cycle loops for FPGA targets??
Reading the help page does not give any hint on that. In contrary:
"x must be a Boolean value or a number. It can be a scalar, array or cluster of numbers or Boolean values, array of clusters of numbers or Boolean values, and so on."
"Boolean functions consume significant FPGA logic resources only when you wire a large array to the input. Consider limiting arrays to conserve FPGA logic resources."
This is ugly.
Will it be supported in the next version of LV (eg LV2010)?
Is there a reason not to support boolean operators for boolean arrays and fixed point numbers or were the NI developers just sleeping?
12-14-2009 11:22 AM
Can you explain specifically what you're trying to do? What logical operator?
I'm just trying to take a shot in the dark and guess what you're doing, bur are you trying to AND (or OR) the fixed point number with a boolean array? You can't do this directly, but you can use the number to boolean array function on your fixed point data and then use that boolean array as an input to the logical operator. This all works in a single cycle loop. This isn't an FPGA or SCTL issue, this is a problem in base LabVIEW as well. I don't think there's a good reason for it, but that's just how it works today.
12-14-2009 11:23 AM

12-14-2009 11:40 AM
I hava a boolean array, lets say of 22 bits and i want, for example, to exclusive-or it with another boolean array of 22 bits, bitwise.
Now I have to convert it to a "blue" (U32) data type to perform this operation, or, sometimes, to take the array appart and place 22 operators on my diagramm.
12-14-2009 01:03 PM
That totally works for boolean arrays in LV 2009. I assume it works for other versions, but that's all I have installed on my computer right now. You need to make sure the arrays are fixed size arrays if you're using array constants or controls. You can do this by right-clicking on the array constant or control (the index part of the array, not an element in the array) and choosing "Set Dimension Size..."
Was that your issue, or is something else not working properly for you? Just to verify, here's the test VI I wrote to verify that this works:
12-14-2009 09:52 PM
i created your example in 8.6. not a broken arrow but will not compile. you get
"The selected function does not support arrays and/or clusters as inputs when used in the single-cycle Timed Loop.
Unbundle clusters and/or index arrays to reach scalar datatypes or replace the single-cycle Timed Loop with a While Loop."
while i may not like these compromises in fpga, we just work around them.
12-15-2009 08:41 AM
"FPGA" means "field programmable gate arrays". I would like to implement arrays of logical gates (simply)!!
I was programming for half a year my new LabVIEW FPGA application, tested every part in simulation mode and every thing worked fine. Now I wanted to compile and realized that it is not supported that way. It took me two days to work around, no big problem but the code is not as nicely readable anymore, just ugly.
I can understand that internally logical operation with arrays are represented by a loop and therefore not compatible with the single cycle loop. The same is true for the rotate array operation. The rotate left and right works for fixed point numbers.
There is nothing I can not implement, it is just about how does LabVIEW allow me to graphically represent the logical operations. I just need to calm down and would like to have reconfirmend that NI indeed was sleeping or if there is a principal reason why this should not be possible to represent logical operation in that way.
And also I would like to know if this will be changed in future version of LabVIEW FPGA or it is better to directly switch to VHDL...
anyway it helped to talk about it 😉 And Labveiw scriting could be an option to "flatten out" array operations...
12-15-2009 10:40 AM