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high speed event counting

I am looking to count events where an event is defined by 1 ttl pulse of 30ns (A newer device allows for 3V 9ns)  I prevoiusly used the6602 but am looking to make a standalone singleboard rio application.  When talking to some engineers this I was told that this was possible, but looking at the spect there needs to be a 100ns min pulse width.  Are there any work arounds?  Is it possible to add sme chip as a prescalar to the input (divide by 10 highspeed counter?)  I am stuck and am ready to meke some hardware decisions.

 

Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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I wanted to post this in the counter hardware board, how do I move a post?
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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"I wanted to post this in the counter hardware board, how do I move a post?"

 

I don't think you can, however under the options you can report it to the moderator.

Have a great New Year!

Now Using LabVIEW 2019SP1 and TestStand 2019
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falkpl,

 

As I am not certain if a moderator can move a post, the best way would probably be to re-post the question on your desired board. Be sure to post a link here to the new discussion. You generally want to avoid double-posting, but as long as it is clear that this discussion was moved to another place, most people will forgive you. Smiley Happy

 

Now, assuming you have not posted elsewhere, I will comment on your issue. The sbRIO's have IO pins that allow you to connect right into the FPGA. As you have found, the manual guarantees a 10 MHz rate and states you can get a bit faster if you are acquiring a single 3.3 V signal.

 

To get even faster, you may have a few options.

  1. Use a deserializer to break up one high speed signal into multiple slower signals.
  2. A similar idea which will not require external hardware, but maybe a bit more programming is to read the same channel on several inputs with slightly staggered start times. This post discusses the idea a bit more.
Good luck, let us know your thoughts and how it turns out.
---

Peter Flores
Applications Engineer
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Thanks I will look at these options.
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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