how can I communicate the fastest way between my FPGA and my host VI

[trajkan]

I would want to send analog signals to my host for further processing, about every 10 microsecond. It is very important that the FPGA sends this values to the host at the right moment. If it is possible which way is then the best to do this?

[Jimmie_A.]

Hello!

I cannot say whether it will work or not since the network communication that is needed here is dependent on so many factors which are not possible to control.

You want to transfer data often and with very short periods of time between each package of data.

If your host VI resides on a Windows machine that application won’t execute deterministically but if you instead would run your host VI on a LabVIEW Real-Time target and then just develop a user interface VI that will run on your Windows machine to present the data this would be the best solution and you wouldn’t be that dependent on the speed of TCP/IP, UDP and such since all processing can be done on the RT target. The data transferred from the FPGA and RT will be done by RT FIFOs.

Please read this article for more information:

http://zone.ni.com/devzone/conceptd.nsf/webmain/91F92C8E4585F16986256CFE005FE6B7

Regards,
Jimmie A.
Applications Engineer, National Instruments

[Pratima]

Hi,

       I read this thread really very enthusiastic query for me also.thats why i am also interfering in this thread.I have achieved to transfer data from FPGA to RT @6.4 MBps using DMA FIFO deterministically.I also transfer data from TCL to NPL through local shared variable with RT fifo (not network).now my query is that i want to transfer the data using TCP/IP protocol to my host PC very deterministic way.at the lower rate i am able to synchronise to transfer data.

                when i used higher rate (max=6.4 MBps),i have to increase the size of DMA fifo(RT side),and also RT FIFO(shared variable ).but my TCL loop will slow then there would be chances the lost of data from NPL to Host.

If my query is clear for you,feedback me otherwise i would explain in much more way.

Pratima

[Van_L]

Hi Pratsha,

Like jimmie said, the transmission of TCP/IP is very indeterministic.
Please specify your minimum transfer rate. If you are hoping for it to be as deterministic as the communication between FPGA and RT, it's quite impossible

Please provide more details

Thank you