how can i decide the depth of all3 DMA fifo's are used as target to host at RT contoller side(host)?

[Pratima]

Hello,

      I am using all DMA fifos,I want to acquire data from 3 AI modules upto 50 khz frequency.Sampling rate can be varied according to application.

   please suggest me how should i allocate memory of my RT controller for those DMA fifos?I am also facing one problem, I am using 3 time deterministic loop with different different priorities,each time loop has one fifo where data is reading with polling method(first fifo.read=0 then againg fifo.read=remaining elements).and each time loop has been interact to host vi with global varibales.those global variables data update from normal time loop.can anybody suggest that this procedure is right or not.if my problem is not much clear i will again explaing my query with snapshot of my application.

Pratima

[MehakD]

You wouldnt need to allocate memory separately on your RT Controller for the FIFOs. You need to create a FIFO under your FPGA target and use the FPGA interface VIs in your RT VI to access the DMA FIFO. You would need to use the FPGA interface invoke method VI to access your DMA FIFO.

As for the other questions, I would recommend you to create a separate post the RT section of LabVIEW so that you can get a faster response to your questions.

I hope this helps!

[NIJanell]

Message Edited by NIJanell on 05-21-2008 05:23 PM