myRIO FPGA LUTs resources

[a_rueda]

Hi,

I had some code and I run out of resources when I tried to flash it in a myRIO 1900. After that, I literally flashed an empty .vi and these are the compilation results:

Anybody knows why is this happening? 47,5% of Slice LUTs seems a lot for an empty .vi.

Is there any extra functionality that I can deactivate to reduce this utilization? 

[MaxJoseph]

You would think that a blank VI would not use any resources, wouldn't you? After all there are no functions and no inputs and outputs. What is using this space? Will this space always be used?

In reality, though LabVIEW FPGA is doing a lot behind the scenes; you see a blank VI but LabVIEW FPGA needs to do things like implement bus logic to handle communication over any interfaces. Basically, you might be asking for nothing, but LabVIEW FPGA needs to be ready to provide all the things made available in the FPGA tab in your project.

You say you are having problems fitting your design on the FPGA. There are some tips and tricks that could be done to make your design fit. First question: How much are you over? Are you 105% utilised or 150% utilised? Second question: Can you post your code?

[a_rueda]

Hi,

I'm currently at 114.6% of utilization. I have a CLIP module that according to Vivado needs around 17.45% of the Slice LUTs. In the next code, if I use user-defined variables for the inputs of the CLIP(pi00 to pi17) everything fits in the FPGA, but when I try to read an analog value and do the following conversion, I exceed the maximum of the resources.

[GerdW · Accepted solution]

Hi a,

do all that math equations using FXP datatype - or keep completely integer values.

This will greatly reduce needed FPGA fabric...

[cbutcher]

As an example, your conversion from AI0 features multiplication by 5 then division by 2^12. Using FXP as suggested and taking care that the FXP size is large enough (possibly LabVIEW does this automatically with a FXP multiplication - be careful if using integers instead), then shifting 12 bits should get you to a suitably framed FXP number (with suitable precision and maximum range) and then you might save some space.

Since you're not using a SCTL, it might also be possible (I think it's possibly possible inside a SCTL too, but I expect only if it unrolls the code...) to use a For loop and then perhaps the compiler can reduce the necessary fabric by a factor for ~3 for that calculation (*5, /4096).

I'd be curious to know what the difference between *5 and /0.200000000(0?)29802 is, especially when rounded back to I32 later. Does it change the value? How much? Is it an acceptable error?

This snippet gives me either 0 or 1, but perhaps that's not good enough.

[a_rueda]

Thanks for the tips! I was finally able to fit everything in the FPGA. the /0.200000000(0?)29802 value was automatically corrected by Labview, I wanted to input 0.2, so 5 is better. Thanks again!

[ibrncfe]

Hi all,
This is an example which I made, I faced the same problem when I moved my vi FPGA file from sbRIO to MyRIO, This attached file is part which I did, I controlled 11 servos and measured accelerometer. the problem was fixed by using a FPGA template file and changed data types on the added blocks into FXP and I16.

I hope it helps. good luck

ibrahim i. n.