notch filter express vi on FPGA

[University_of_Adelaide]

I tried to use a notch filter to remove some of the mechanical resonance (25Hz) in the encoder feedback. However, the notch filter express vi on the FPGA showed me some unexcepted results. When filter input is a constant, the filter output showed me a very large offset compared to the input. Sometimes, the output might keep changing and oscillating in a low frequency. This really doesn't make any sense for me. If the filter input is a constant, the output should be the same constant as the only components in the input signal is DC (unity gain at 0Hz). I think I defined all the parameters properly. The FPGA clock is 40MHz. The expected sample rate is 10kHz which is equal to the loop rate the filter is running. The cener frequency is defined as 25 Hz and the bandwidth is defined as 5 Hz. The input and output are both in the format of integer 32. Has anyone used notch filter express vi on FPGA before? BTW, I also used the low pass filter express vi on FPGA  to filter the D term of the PID controller. The low pass filter works properly with a cut off frequency of 500 Hz. The other parameters are defined as the same as the notch.

[JLewis]

You're most likely seeing quantization effects arising from a combination of wide inputs (32 bits) and a challenging notch design, where the notch frequency and bandwidth are low relative to the sample rate. Covering the full dynamic range of a 32-bit data path can get prohibitively expensive, so the filter is optimized to handle full-scale signals with reasonable relative accuracy. The tradeoff is that small input signals may exhibit the oscillations and offsets you describe. Here's a few options:

1. Raise the notch frequency and/or lower the sample rate. The Rational Resampler allows you to adjust sample rates without aliasing.
2. Use a smaller input type. The relative accuracy increases roughly linearly with each bit of input width reduction at the high end. You may have to do some upstream scaling or saturation to ensure that your signal fits in a smaller path.
3. It is possible to convert the Express VI to a standard subVI and edit the code to use wider internal datapaths. This is not recommended unless you're comfortable with fixed-point arithmetic and prepared to do some testing.

[University_of_Adelaide]

Thanks, mate. This makes perfect sense and is very helpful for me.