I'm using Lab View 7 Express on a Windows 2000 machine.
I need to control three data pins in the parallel port; clk, data, and sync. When sync is taken low the board is informed that a word is being written to the device. The first bit is read into the device on the next clk falling edge with the remaining bits being read into the device on the subsequent clk falling edges. sync frames the 16 bits; therefore, when 16 clk falling edges have occured, sync is taken high again.
I have been working on this problem for about a week, and cant seem to make any progress. If anyone could help with a sample VI or any ideas, I would be extremely greatful. Thanks for the help. Let me know if you
require more information.
Attached is a copy of the spec sheet that came with the board. It is a .pdf