pc rt vi nothing shows up on tdms and graph

[alex8624]

good evening! thanks to the help of a lot people from this community I was able to reach this stage, but still I'm not able to see anything on the graph neither on the tdms file.

what I'm doing is acquire a voltage signal every 5 ms that I will put on the controller on the pc main; then I start the pc main vi, but nothing change... i can't see anything. I need to acquire the voltage signal every 5ms for at least 3 hours.. I hope someone can help me, because I'm trying to read everything from this type of things from 3 weeks but still no progress and I dont have any collegues to disscus with.

I attach the project.

[wiebe@CARYA]

My guess is that either the RT isn't started, or that the FPGA isn't started, or that the FIFOs need to be started\initialized.

You'll have to take care of that yourself, as there are use cases where that shouldn't happen automatically.

 Start validating peace by peace.

Either top to bottom or bottom to top:

• Is the FPGA actually acquiring data?
  • Add an indicator and read it, or put the loop counter on the FIFO.
• Is the FPGA sending data to the RT?
  • Validate with for instance the loop counter.
• Is the RT sending data to the PC
  • Use a random number.
• Are there any errors?
  • Check the TDMS error outputs and the shared variable error output.

If any of these parts are not working, you'd get 'nothing' (zeros?) in your graph and TDMS.

[XM43]

Hi Alex,

Here is my theory,

1) You are either running only VI that runs on PC or FPGA or Just the RT one.

2) You modified project that I sent you in your last thread and changed it into something else.

3) and you do not like wiring error terminals.

Here is what I think you can try:

1) Use the last project that I sent you or the new one attached (if using new one, make sure you add your target in the project and copy VIs and library under right category)

2) Compile FPGA VI again for your target

3) Make sure Open FPGA VI is configured properly on RT VI

4) Once you have successfully completed steps above. Run the RT VI first and then RUN the PC vi.

5) To make sure it is working, I have wired a control "Element" on the RT VI which sends value to FPGA VI. Now if you see this value change on the PC VI (in graph) (Which it should) then it is working.

6)Then you just have to delete that "Element" control form FPGA VI and wire it with Analog input terminal.

[alex8624]

thank you Xonmyth, now I have seen the importance of the "error" when I try to run the rt main vi, it stops and an error shows up " code 61003" niLvFpga_run_dynamic.vi and I dont know what to do.. I attach the project

[alex8624]

I changed the global variable of stop in the rt main with a stop button and it worked, now I try to see if i can acquire.. 

[alex8624]

but now I have another problem the graph... I cant see the time but only 1 data at time

[GerdW]

Hi Alex,

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@alex8624 wrote:

but now I have another problem the graph... I cant see the time but only 1 data at time

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That is the amount of data that you provide to your graph!

When your data only contain one sample then the graph will display just one sample…

(Basic LabVIEW stuff: did you take the Training resources?)

[alex8624]

yes I have read everything I found about fpga, rt and fifo, but still It's still too difficult, for me, to do it alone. from what I have understood that kind of fifo structure give me the possibilite to read "istantaniusly" the data without having a limit on the numeber of element, so I dont have elements remaining.. dont knowing the right numer of elements i need to store or the total time, I'm kinda lost.. I dont know if I was able to explain myself correctly.

[wiebe@CARYA]

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@alex8624 wrote:

yes I have read everything I found about fpga, rt and fifo, 

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But... Did you do the basic training?

Change the graph to a chart, and it will show a history...

There are 100 other ways to change this to what you want. But it's hard to advice without knowing what you want.