06-15-2012 08:31 AM
Hi,
I am learning about pipelining and I have a few questions I was not able to answer.
I implemented simple subVI which is used inside SCTL. Inputs and outputs are arrays with 15 items.
a) when this code is run the output array with results is shifted (rotated) by 2. When feedback nodes are removed it runs correct. Why ???
b) in the code I have seen, there was a little bit different icon for feedback node than here. Here we can see a star below the arrow but in web pages there is a dot below arrow. Do I use wrong feedback node ?
 
06-15-2012 08:41 AM
06-15-2012 10:28 AM
What does BD mean ?
06-15-2012 10:32 AM
BD = block diagram
06-15-2012 10:41 AM
Well 🙂 Anyway I do not have a clue how to change the feedback nodo to forward node for pipelining
06-15-2012 10:59 AM
Right Click. Change Direction.
06-15-2012 11:09 AM - edited 06-15-2012 11:11 AM
It seems like it's working correctly to me. I haven't paid close attention to the algorithm, but the code seems to respond as expected after I've executed it three times.
Pipelining works by taking an algorithm and essentially splitting it into concurrent sections. This allows us to increase the overall frequency at which we can operate the logic because we're decreasing the overall propagation delays for signals to traverse between clock edges. Longer paths mean we have to operate the logic at lower frequencies, so splitting the path into different concurrent sections means that we can go a lot faster. The drawbacks of pipelining are that initially, there's some latency involved, because although we're splitting the code into individual pieces, they still rely on sequential output from a previous section. In this example, when we first run the VI all of the Shift Registers are uninitialised, which means that they'll pass out garbage values; this is the latency. On the second iteration, the first feedback node posseses valid data from the previous iteration, but the second set still has garbage data that is has been passed from the first iteration of the previous register.
After that next run, real data values have finally propagated through all sections; we're getting valid data, albeit delayed data. Usually in digital design, this isn't a huge price to pay when considering we can drive the complete algorithm a whole lot faster.
In short, removing the feedback nodes is removing the intermediate registers, giving us our one long path with immediate data output. Introducing the feedback nodes is what gives us that latency.
06-15-2012 02:34 PM
Well. I changed the code a little bit. When the input array is e.g. 1,2,3,4,5,6,7,8,9 and offset array zeros than after one run the ouput is 0,0,1,2,3,4,5,6,7..
it is correct ? I want output 1,2,3,4,5,6,7,8,9....
06-15-2012 02:45 PM
Yes. As you've been told, those feeback nodes are introducing a delay of two iterations in the results.
All you need to do is use array subset or delete from array to remove the first two elements of your output array.
06-15-2012 02:56 PM
I think I have found the solution. I missed feedback nodes for index. When I added two feedback nodes to index wire the code was running ok.
Thanks guys for help and ideas.