queries regarding DMA FIFOs

[prashiit]

Hello..

           Can anybody send an example of DMA FIFO. This example should give an array of data to a DMA FIFO in host VI. This array of data should be read in the FPGA VI. The array of data is processed in the FPGA. The resultant array should be available to host VI.

I have seen some examples. But there is only one way transfer of data. In my case I need two way transfer of data (host VI to fpga VI and FPGA VI to host VI) using DMA FIFOs.

I tried do develop a simple example. I created two FIFOs. one is host to target (FIFO1) and another is target to host (fifo2) . I have given array of data to a host to target fifo(FIFO1 write) in hostVI. these array of data is read in FPGA VI using same FIFO1(read). I added the array with 5. I connected the re sultant array to FIFO2(read) in FPGAVI. Now, i have to read the output array in host VI. BUt, when I drag the FIFO2 in host VI, it is becoming FIFO write instead of FIFO read.

 and FIFO properties are automatically changing to Targe-scoped FIFO...

What I am doing wrong..

Please help me

Thanks

Prashh

[Ruhmann]

What version of LabVIEW are you using?  (you might want to get in the habbit of always posting your LabVIEW version)  I think all you need to do is drop an invoke method from the FPGA Interface pallette.  Connect the reference to your open node.  Then select the FIFO2.read method.

This is from LabVIEW 2009, but you should see something similar in other LabVIEWs.

 

[prashiit]

Hello Ruhmann,

        I am using labview 8.6.   I created a new project and created two fifo under fpga target. I selected target to host fifo and host to target fifo. But, After creating fifos, if I open them, they are showing targed scoped (which disabled) in the cofiguration dialog box.

I dropped invoke method connected reference and when I click the invoke method, fifo option is not coming.

[Vaibhav_Vashisht]

Hi,

I think I've done what you say you've done. I don't face the same problem as you do. Check the jpg file attached.

Vaibhav.

[prashiit]

I have seen ur jpg file. you are using cRIO fpga kit. I am using Spartan 3e FPGA kit.

Will the problem come with that. How many FIFOs does spartan 3e support...?

Thanks

Prashh 

[prashiit]

Hello vaibhav,

 Can u send ur VI.

Thanks

Prashh

[Vaibhav_Vashisht]

Hi,

Here it is.

Regards,
Vaibhav.

[julesjay]

HI,

I've also got some questions concerning DMA FIFO and in particularly timeout parameter of FPGA to HOST DMA.

On the FPGA side should I choose -1 or 0?

The question is :  If I put 0 as timeout as the DMA FIFO is full, is the oldest element lost?

Thanks.

James

[Ravi_Shankar]

By choosing "-1" you disable the DMA FIFO's time out.

By choosing "0" you asking the operation to time out as soon as the FIFO is full meaning no wait

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The question is :  If I put 0 as timeout as the DMA FIFO is full, is the oldest element lost?

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Once the FIFO is full; it does not over write.

It does not add new element.

So it's lossy.

Regards.

[Ruhmann]

Prashiit,

I assumed that you were using one of NI's standard FPGA targets such as cRIO, R Series, or FlexRIO.  I actually don't know enough about the spartan 3e academic product to tell you for sure, but it doesn't look like that product supports DMA FIFOs.  Is there documentation installed on your computer that might clarify this?