question about FPGA two loops

[lightmiddle]

Hi there :

 I am using PXI 7833 R card and Labview 8.0 for windows xp and Labview FPGA 1.1.

I used two loops in a program . I set the inner loop period at 5 ticks so the outer loop period should be 32x5=160 ticks. However when the inner loop finished executing 32 iterations and the outer loop called the inner loop again. there is a delay . this delay makes the output pulse width wider than the other.

I am wondering if there is another way to generate the signal such that  the delay can be avoided?

Message Edited by lightmiddle on 03-06-2006 05:30 PM

[Ame_G]

Hi there,
I think you are using LabVIEW 8.0 with FPGA 8.0 not 1.1.
Here is an example VI that will show you how to do pulse generation with single cycle timed loop. It generates a clock signal at one of the digital lines of R-series FPGA. The program uses Single Cycle Timed Loop (SCTL) as opposed to the common use of while loops, which will take at least 3 ticks to execute. The user can control the frequency of the clock by changing the 'Number of Ticks' in the front panel while the program is running. The frequency of the clock can be calculated by Freq. Generated Clock = Compiled Frequency/(2 * Number of Ticks). The minimum value of the Number of Ticks is 1.

Ame G.
National Instruments

[lightmiddle]

Hi buddy :

Yes, I am using Labview 8.0 and FPGA 8.0. 

I am talking about two loops problem. Sure I know how to use SCTL . What I need is to use two loops. can you do it using two loops?

Message Edited by lightmiddle on 03-13-2006 12:55 PM