A general question regarding vi-priority inheritance:
In the LV 2012 example project 'LV FPGA Waveform Acquisition and Logging on CompactRIO', in RT Main.vi, the RT Loop - Acquisition and Logging.vi has 'Normal' priority and runs in parallel to the other vi's (RT Loop - UI Commands-, Watchdog-, System Health and Monitoring etc.). Its subvi 'Acquire and Log Data.vi' and its subvi 'Acquire Data.vi' , which does the actual DAQ and Logging both have 'High' priority as they should.
In the NI help there is mention of 'Priority Inheritance', but the text focuses on when the subvi as a lower priority than the calling vi and then gets bumped up. What exactly happens when the subvi has higher priority than the calling vi? As the calling vi has 'Normal' priority and runs in parallel to the other RT Main.vi subs does is wait for its turn or does the fact that it contains a high priority subvi bump its priority up as well so that it will move to the head of the execution queue whenever DAQ has to be performed?
