register vs wire on FPGA

[Intaris]

Can anyone comment on the practical differences (placing, routing, efficiency, resource requirements) on the two different pieces of code below.  AFAIK they should be functionally equivalent butd oes separating the funcitons into different loops allow for bettwe or worse optimisations...... I current have a lot of the first type of structures (register-based "processes" on FPGA)

Shane.

[Dragis]

In theory those two register implementations should be identical. However, it can be very hard to tell whether they are because there is so much other logic associated with having separate loops, etc. Are you noticing that one scenario is impeding your application somehow?

[Intaris]

No, it seems to be working OK, but I was just curious because the architecture will be moving towards production code in the near future.  Just wanted to have a second opinion so to speak.  My original idea was that splitting up into multiple loops would actually aid placement since the local "modules" are smaller,a llowing for a finer placement within the device.  I have absolutely no idea whether this logic holds water or whether it won't actually hinder progress ultimately (if the logic for the loop itself becomes expensive).

Shane.

[Dragis]

Most likely the placement of the registers won't affect the design so much as how it allows you to break up the core logic kernels into separate pieces. If it makes sense to break the logic into separate "actors" that communicate via registers that is a perfectly valid way to program.

However, one overall design philosophy you might want to consider is when you do have separate concurrent processes make sure you don't actually need FIFOs to properly synchonrize them. Especially if you need to run the loops at different clock rates.

[Intaris]

Yeah, I ran into the Register vs Clock boundary problem a while ago.  Had to solve it with Block RAM FIFOs (Hugely inefficient with sub 1% BRAM usage int he block I allocated, but do-able).

Once I trimmed out any erroneous clock boundaries things work fine (or seem to at least).  I currently have 6 "actors" running in parallel with the registers describing the "API" between them.  Seems to work OK, but compile times have gone up and I've started to get timing errors, so I was re-evaluating whether this is such a good idea or not.

Of course, I also have more code in there than before, so that might explain the longer compiliation times.