rt / how can a fpga-bitfile be exchanged without recompile the rtexe?

[Lars.B]

Hello to all,

maybe someone of you knows the trick:
my program have two parts, one is running on RT-OS (LabView RT/PharLap) the other part is on a FPGA. For programming I'm using LV 8.5.1.

In the VI (on RT) which calls the FPGA, is a static path-reference on the bitfile. Idea of this was that the bitfile is dynamically loaded by every start of the RT and when there are bugfixes to do in the FPGA-code, then this could be done with an simple exchange of the bitfile (which I can send to the customer and he replaces then byself the file per FTP).
In fact replacing of the bitfile does not have any effect, it seems that the bitfile is integrated in the RTexe and so cannot be exchanged on harddisk. Only way to replace the bitfile seems to recompile the RTexe with the new bitfile.

Does anyone knows how this can be solved? Or is there no way to do so that a bitfile is loaded at runtime (as a file and not integrated in RTexe)?

Or is this maybe because the VI which calls the bitfile, is forced to be part of the compiled RTexe (build options)?

Greets,
Lars

[TBalazs]

Hi Lars,

as far as I know there are 2 ways to dynamically download a bitfile to an FPGA device.

1. Using the NI-RIO driver (available at: http://joule.ni.com/nidu/cds/view/p/id/993/lang/en)

When you install the NI-RIO driver, the RIO Device Setup utility is installed, which allows you to download bitfiles to the flash memory of your FPGA device. After that when the device is reset or powerup, the device itself can load and start this new bitfile. Just make sure that the option "Autoload VI on device powerup" or "Autoload VI on device reboot" is set accordingly under Device Settings in the RIO Device Setup utility. Change these options of the device so that the bitfile is loaded on a reset or power loss, then reset or cycle the power for the device.


2. Using the FPGA Target System Replication utility as discussed under: http://zone.ni.com/devzone/cda/tut/p/id/6465

With the help of the VIs included in this utility (http://digital.ni.com/public.nsf/websearch/AF4FF0C65AF31B4348257337006A144A?OpenDocument) you can basically set the same options and select a bitfile similar to the RIO Device Setup utility of the NIO-RIO driver. Similar to the RIO Device Setup utility you can download your bitfile to the flash memory of your FPGA and then reset or power cycle your device.

I hope this information helps you.

Best regards,

Balazs

[JMota]

Hi Lars,

---

@Lars.B wrote:
Does anyone knows how this can be solved? Or is there no way to do so that a bitfile is loaded at runtime (as a file and not integrated in RTexe)?

Or is this maybe because the VI which calls the bitfile, is forced to be part of the compiled RTexe (build options)?

---

Loading a different bitfile at run-time is not supported, as the Host VI (RT VI) needs to know beforehand the information about the bitfile in order for you to write a VI that access the resources of the FPGA VI/bitfile, such as controls and indicators.

You will have to re-create the RTexe anytime you make changes to the FPGA VI.

What Balazs suggested would work if your RT VI didn't do an Open FPGA Reference. That is because that node has the bitfile embedded on it and will download it anytime it executes if a different personality (bitfile) is on the FPGA. That's the technical reason on why replacing the bitfile on disk on RT has no effect, as you have already figured out.

JMota

[Berla]

I had the same problem with the use of the PCI-7813 fpga board.

What i did was to rename the bitfile to ex. active.lvbit in the VI calling/open the reference to the FPGA board and before executing the code I copied the bitfile I wanted to use to the name active.lvbit, This only works without recompiling the VI calling the FPGA bitfile if no changes made to the frontpanel of the FPGA code, just changes/bug fix ib the FPGA code.

[Salac]

I am using cRIO with the following configuration: cRIO-9012, cRIO-9101, NI 9233, 9237, 9203 and 9219. My application is datalogger and data is logged direct to the USB flash. Max sample rate is 2kS/s on each channel, so I made a few configuration so that I logged from 9233 with for example 10kS/s. I made 5 differrent FPGA vis and compile it and so I have 5 different bitfiles (and 5 rtexe). RT vi is same for all. When I put vi for one configuration and its bifile in the Project and deploy RT from Project everything works OK, for all 5 configuration. For customer I make enum with 5 items so when he choose a configuration rtexe file is being copied from corresponding folder. I used RT replication tool and copy rtexe from folder. But, then it is not working. For example for configuration where I use only 9233 I got more datas (4 times more). Does anybody know what's the problem?