sequence structure compiled for FPGA

[deceased]

The flat sequence for enforcing execution order is common, My guess is the compiler adds some flip flops to force the order at the expense of clock ticks.

I come at it the same way as you. Anything that can be in an SCTL will be. Get rid of the enable chain and save time and resource utilisation.

[richjoh]

Gentleman thanks for chiming on the topic, makes sense to use SCTL and the compiled FPGA is a black box.  Excellent contribution to question.