share values between two DAQ cards (one used as FPGA)?

[Seiji_ANU]

G`day,

I`m using an FPGA 7853R card to implement some feedback control of an optical system. Specifically, I`m locking multiple cavities using simple homemade Labview PID controllers.

In my code, each cavity that I lock requires two inputs (an error signal, and a DC signal of the output so that I can monitor the lock point) and one output from the software PID output that controls the system.

Therefore, since the 7853R card has 8 inputs and 8 outputs, I can currently lock only 4 cavities by using all 8 inputs on the card and 4 outputs. I`d like to be able to lock 8 cavities on one FPGA card. 

Now here comes the question, we also have a PXI-6251 DAQ card lying around, which I thought perhaps I could use to input the DC monitors, freeing up half of the inputs on the FPGA card, so that I could control 8 locks on the FPGA card.

Is there a good way to implement this? I`m relatively a beginner to Labview, and thought if I could have two VIs running concurrently, perhaps I could share the DC monitors on the PXI-6251 as Global variables? Or is it possible to write one VI that references two cards - both the 6251 and the 7853?

Ultimately, we have 24 locks, so it would be great if I could free up as many inputs on the FPGAs as possible (as the 1033 chasis can have 5 cards and so we could have 4 FPGAs.

I should mention that the signals in question are below the sampling rates of roughly 1Mhz on both cards so no dramas there.

Hopefully this kind of thing is routine in coding, and perhaps someone has a good idea how to do this efficiently?

Please ask me if I`ve left out any vital information!

[Kareem_W.]

Let me first preface my comment by stating that my assumption is that you would like to use your 6251 for your inputs and the 7853 for processing and output.

While it is possible to acquire data with the 6251 and use a FIFO to send it to the 7853 (over DMA), you will face a couple of challenges:

1. You will need to use a host VI to manage data flow between the two cards. In other words, you cannot stream data directly (peer-to-peer) from the 6251 to the 7853 - neither card supports this function. This means that the data will be software timed once it inters the host VI.

2. Additionally, the maximum sample rate on the 7853 does not meet your requirement 1 MS/s (1 MHz). The 6251 can sample up to 1.25 MS/s but the 7853 can sample up to 750 kS/s.

What these two mean is that your application will not be deterministic (your sample rate will not be stable) because Windows is managing the process, and you can't achieve the sample rate of 1 MS/s because the 7853 won't keep up.

Please let me know if my assumption is incorrect.

Regards,

[Seiji_ANU]

Dear Kareem,

Thanks very much for the quick reply. You`re spot on with the assumption. Right now I am using the 7853 to input 8 channels (4 error signals and 4 DC monitors) and to output 4 software PID outputs. And yes, I would like to use the 6251 to read in the inputs, and use the 7853 for processing and output.

The FIFO sounds like the way to go, I`ve practised writing a host VI which opens up my master VI (that reads in 7853 inputs and computes outputs) and I`ve been able to manage data flow between the VIs using your suggested FIFO read and write methods. It works a treat, I`m quite stoked.

I will now try to add another FIFO to manage data flow between the 6251 as well, I did not know this was possible. You`re right about the clocking issues... what if I put in a delay of some sort (perhaps in one window of a case structure) to slow down the VI controlling the 6251, so that it doesn`t run at 1.25MS/s but instead at 750 kS/s? Then pehaps the two cards would be in sync.  

My other question is relatively simple: Can I sample all 16 analogue channels on the 6251 without paying a sampling rate penalty? It wasn`t entirely clear to me if the advertised "scanning rate" of 1MHz for the 6251 means that I could sample all channels simultaneously at 1MHz or that each channel would be sampled at 1MHz but it would have to "scan", so that if I used 10 channels for example, the overall sampling speed for the VI to sample all channels would be 100kHz (1MHz/10)...

I`ll have access to the 6251 next week (it is currently in use by another researcher) so can test everything out, but I`m trying to write the code now so I`m very grateful for your help and suggestions. Thanks.

[Kareem_W.]

I checked the spec on the 6251 and found that it is NOT a simultaneous sampling card. This means that the sampling rate will decrease as you increase the number of channels.

As for your second question, yes you can slow down the 6251 to try to sync it with the 7853, but there are two challenges there:

1. The reduced rate will fall below the 1 MHz rate that you stated as your sampling requirement. In essence, the 7851 has a max sampling rate of 750 kHz and the 6251 at 1.25 MHz. Even at the highest sample rate, the 7853 is incapable of hitting a 1 MHz rate. 

2. These two devices run on different drivers. (6251 uses NI-DAQmx, 7853 use NI-RIO) This will make it difficult to sync the two cards because the two devices do not communicate directly with one another. All communication will be in SW. Any attempt to sync begins with a shared clock and a shared trigger. If these are in a PXI chassis, you can try to use the 10 MHz clock on the backplane as a reference clock for both devices. You can also export triggers with PXI. Either way, this will be very tricky to implement.

Regards, 

[Seiji_ANU]

Okay, that's some bad news but I understand now that the sampling rate must decrease since the card cannot sample simultaneously. Thanks for the clarification.

The driver issue is a good point, I hadn't fully appreciated how difficult triggering from clocks can be. I'll play around and if I find a solution I'll post it here in case anyone else is interested.

Thank you very much for your time!