Hello,
The problem is that at the output of the module NI 9263, your sinus doesn't look like to a sinus any more, but it's more a quantified signal. The best you can do is to oversample your signal by 2, by adding a point in middle of 2 points, more exactely by interpolating your signal.
You could do that either by adding a shift register in your while loop, or you can directly use a VI function "linear interpolation" in FPGA Math & Analysis -> Utilities
This should eliminate the high frequency and as a consequence the noise in your loudspeaker.
Best Regards,
Laurent
NI Switzerland