spartan 3e poor performance oscilloscope

[Victor Vlad]

Hello , i am a student and i work on my final year project wich consist in an oscilloscope implemented on spartan-3e board. I have to program the fpga in Labview. Untill now i initialized the PGA on th board, the ADC on the board, and now i have tomake the host program.My problem is the fallowing one: how should i proceed with the samples to build the waveform on the control panel of the host .vi?Because the speed of the fpga's .vi is much faster than the host's one...how should i proceed, please help.

Best regards, 10x in advance .

Victor

[Victor Vlad]

i mean, what can i do, not to lose any sample...do i have to use a FIFO?how can i send more samples one time to build the waveform and to refresh at least 25 times/secound?

[Hesloppy]

Hi Victor,

Using a DMA FIFO is going to be your best solution.  With the FIFO your host will be able to continuously pull the samples from the FIFO without losing any. Then on your host you can build the waveform and append it (Waveform » Analog Waveform » Append Waveforms.vi) to your running waveform.

Best Regards,

[Victor Vlad]

thanks but today i figured out that spartan 3e does not support DMA :(...so i can use regular fifo but in continous sampling i don't know how will i  do it!

anyway, thanks for the attention...

best regards , 

Victor Vlad

[Victor Vlad]

let's assume that i don't make the data aquisition real time, how can i sincronise the data transfer betwen the fpga board and host VI knowing that the execution time of the fpga vi is 9 us and the host's seems to be 350-400ms...

Thank's in advance, Victor

[Hesloppy]

Hi Victor,

What you can do is have the host VI read from the FPGA with the Read/Write control.  It will only be able to read the data as fast as your host computer is running so you will lose data.  There really is no way to synchronize it because the FPGA runs much faster and there is no FIFO available.

Best Regards, 

[Victor Vlad]

But if i make a fifo and use in a flat sequence the fifo write function and in the next sequence i use fifo read function each one in a for structure for n elements, and then read the samples on the host in a array structure and just afre i finish the transmission of all elements i start sampling again, wouldn't that be ok? Will i still loose data?

 Thanks  again, 

Victor

[Hesloppy · Accepted solution]

Hi Victor,

I think if you do it the way you described you should not lose data.  It seems pretty good to me.  Have you tried doing it that way yet?

Best Regards,

[Victor Vlad]

hello, first of all sorry for the solution button, it was meant to be kudos button, anyway, i still have an perplexity, in the read function from the fifo, that is inside a for loop for n elements and all those in a flat sequence, will this function send the elements patient?like the host can receive?or do i have to make a handshaking protocol betwen the host vi and the target vi?

[Hesloppy]

Hi Victor,

You will need to have handshaking in it.  The FPGA will run as fast as it possibly can.  It will not know if the data has been read yet, so you will need to and some handshiking to confirm that you got the data.

Best Regards,