spikes in analog input_FPGA to RT via FIFO

[kumarasova]

Hi, 

when I read two analog inputs using FPGA and transfer to Real time via FIFO, I see my readings are filled with spikes. Has anyone come across this issue?

Attached are the image of the Real time front panel and the program I used. Any help will be appreciated.

[BertMcMahan]

Just a guess (I don't have everything installed to fully open your program) but it looks like your FIFO is getting the values swapped back and forth constantly. I'm not sure why that'd happen, but if you put a known voltage on each of those channels, I bet your spikes would go back and forth between the known voltage on each channel. Put 2V on one and 4V on the other and your spikes would likely line up that way.

What is your Timeout value set to? Anything weird there? What about your wait function on the FPGA? If that defaults to 0 (which I suspect it is) then the FPGA loop will run too fast.

Perhaps your FIFO is set to an odd number of elements and it's getting filled up super quickly?

[kumarasova]

Bert,

1. You are right about the numbers being swapped (see image attached)

2. I have set the time out value to 10.

3. I am using loop timer (which is like a wait function, but in ticks) in FPGA with wait of 10 ticks.

4. The real time program reads, one value at a time from FIFO, therefore the number of elements  remaining in FIFO is always 16382 (see image attached).

may be I can only read as arrays, not as individual values(?), since

(a) FPGA is much faster than realtime program in data acquisition 

(b) Real time is better than FPGA in handling arrays

[BertMcMahan]

It sounds like you're filling up your FIFO if there are always 16382 values remaining in it. Either read more values at a time or write to it slower. You want your consumer to be faster than your producer.

What is your FPGA clock speed? If it's at something like 20 MHz then 10 ticks is still a 2 MS/s sample rate, which is incredibly high.

[kumarasova]

Bert,

1. FPGA does not allow me to use a timed loop, therefore I cant specify the clock speed for the loop. LabVIEW throws code generation error (please see images)

2. I had to use about 10000 tick delay until I see no spikes (or hardly see a spike), which is 2 ksps, terribly slow. MXP analog inputs of myRIO can do 500 ksps. The elements remaining in FIFO is still 16382 though.

3. The workaround I found is, using two different FIFOs for the two analog inputs. This program does not cause any spikes (or value swap) even with 0 tick delay in the FPGA program. I have attached the RT and FPGA programs. 

4. I still have to try reading the values as larger arrays, rather than one value at a time. I will respond back once I try that.

[BertMcMahan]

Your limitation is your RT loop, not your FPGA loop. Your idea to read arrays of values at a time is the right way to go- you just can't take out single elements quickly enough.

[Intaris]

You need to have a FIFO transfer method which accounts for the fact that your enqueuing on the FPGA side will be losing data.

Currently, if your FIFO is always full when reading it, then your FPGA code is TRYING to write values to the FIFO, but they are getting dropped.  If a value for one channel gets dropped, then if the next write succeeds, the FIFO will contain two values from the same input channel in a row.

You need to make sure that if you can't write to a FIFO on the FPGA side, you handle your data transmission accordingly, making sure that your data protocol in the DMA FIFO is maintained.

See HERE for more background info