stale bitfile

[dave-nokia]

When I do a new successful compile of my FPGA and run the project it appears that what actually gets loaded into the FPGA is a bitfile from a previous complile.  I've verified that the bitfile date and time stamp is correct for the most recent compile, I've powered down the chassis and closed Labview completely, and this still happens.  However if I go to the FPGA loader VI and delete the FPGA and recreate it then the correct bitfile is used.  There should be an easier way.

[speleato]

Hi dave-nokia,

I assume you mean you have to delete and re-add the FPGA Open node, is that right?

One option, if your version of LabVIEW has it, would be to use the Open Dynamic Bitfile Reference node. It takes a filename and loads the bitfile from disk as opposed to scripting it on the diagram.

Sebastian

[dave-nokia]

Yes, I have to delete and re-add the FPGA Open node.  If I forced a recompile of the project would that "script" the correct bitfile "on the diagram"?

Dave

[speleato]

No, unfortunately a recompile doesn't cause a re-script.